求解xilinx ISE使用报错的处理——Port <clk> has illegal connections. This port is connected to an input buffer

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用ISE综合时报如下错误：
Port <clk> has illegal connections. This port is connected to an input buffer and other components
clk是我用的系统时钟，作为输入，当然要接input buffer，然而我的工程有很多子模块，当然也要将clk连到各个component，报这个错究竟是啥意思呢？改怎么解决？希望知道的朋友帮忙解答一下，不胜感激！

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