ARM中断分发

General handling of interrupts

The Distributor maintains a state machine for each supported interrupt on each CPU interface. Interrupt handling state machine describes this state machine and its state transitions. The possible states of an interrupt are:

• inactive

• pending

• active

• active and pending.

When the GIC recognizes an interrupt request, it marks its state as pending. Regenerating a pending interrupt does not affect the state of the interrupt.

The GIC operates on interrupts as follows:

1. The GIC determines whether each interrupt is enabled. An interrupt that is not enabled has no further effect on the GIC.

2. For each enabled interrupt that is pending, the Distributor determines the targeted processor or processors.

3. For each processor, the Distributor determines the highest priority pending interrupt, based on the priority information it holds for each interrupt, and forwards the interrupt to the CPU interface.

4. The CPU interface compares the interrupt priority with the current interrupt priority for the processor, determined by a combination of the Priority Mask Register, the current preemption settings, and the highest priority active interrupt for the processor. If the interrupt has sufficient priority, the GIC signals an interrupt exception request to the processor.

   Note

   Throughout this document, an interrupt is described as having sufficient priority if its priority value, compared with the Priority Mask Register value, the preemption settings for the interface, and the priority of the highest priority active interrupt on the processor, mean that the CPU interface must signal the interrupt request to the processor.

5. When the processor takes the interrupt exception, it reads the ICCIAR in its CPU interface to acknowledge the interrupt, see Interrupt Acknowledge Register (ICCIAR). This read returns an Interrupt ID that the processor uses to select the correct interrupt handler. When it recognizes this read, the GIC changes the state of the interrupt:

   • if the pending state of the interrupt persists when the interrupt becomes active, or if the interrupt is generated again, from pending to active and pending.

   • otherwise, from pending to active

   Note

   • A level-sensitive peripheral interrupt persists when it is acknowledged by the processor, because the interrupt signal to the GIC remains asserted until the interrupt service routine (ISR) running on the processor accesses the peripheral asserting the signal.

   • In a multiprocessor implementation, the GIC handles:

     • SGIs using an N-N model, where the acknowledgement of an interrupt by one processor has no effect on the state of the interrupt on other CPU interfaces

     • peripheral interrupts using a 1-N model, where the acknowledgement of an interrupt by one processor removes the pending status of the interrupt on any other targeted processors, see Implications of the 1-N model.

6. When the processor has completed handling the interrupt, it signals this completion by writing to the ICCEOIR in the GIC, see End of Interrupt Register (ICCEOIR).

   The GIC requires the order of completion of interrupts by a particular processor to be the reverse of the order of acknowledgement, so the last interrupt acknowledged must be the first interrupt completed.

   When the processor writes to the ICCEOIR, the GIC changes the state of the interrupt, for the corresponding CPU interface, either:

   • from active to inactive

   • from active and pending to pending.

   If there is no pending interrupt of sufficient priority for the CPU interface to signal it to the processor, the interface deasserts the interrupt exception request to the processor.

   A CPU interface never signals to the connected processor any interrupt that is active and pending. It only signals interrupts that are pending and have sufficient priority:

   • for SPIs, this means the interface never signals any interrupt that is active and pending on any CPU interface

   • for SGIs, the interface never signals any interrupt that is active and pending on this interface, but does not consider whether the interrupt is active and pending on any other interface

   • any PPI is private to this interface and the interface does not signal it if it is active and pending.