8259a 的地址 0x21 和 0xA1 的作用
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0.12完全剖析讲的有点出入，下面的是正解：
转自：
http://cs.smith.edu/~thiebaut/ArtOfAssembly/CH17/CH17-3.html
另外这个系列文章貌似不错，收藏以后慢慢看：
The Art of Assembly Language Programming
http://cs.smith.edu/~thiebaut/ArtOfAssembly/artofasm.html
17.4 Hardware Interrupts
Hardware interrupts are the form most engineers (as opposed to PC programmers)associate with the term interrupt. We will adopt this same strategy henceforthand will use the non-modified term "interrupt" to mean a hardwareinterrupt.
On the PC, interrupts come from many different sources. The primary sourcesof interrupts, however, are the PCs timer chip, keyboard, serial ports,parallel ports, disk drives, CMOS real-time clock, mouse, sound cards, andother peripheral devices. These devices connect to an Intel 8259A programmableinterrupt controller (PIC) that prioritizes the interrupts and interfaceswith the 80x86 CPU. The 8259A chip adds considerable complexity to the softwarethat processes interrupts, so it makes perfect sense to discuss the PICfirst, before trying to describe how the interrupt service routines haveto deal with it. Afterwards, this section will briefly describe each deviceand the conditions under which it interrupts the CPU. This text will fullydescribe many of these devices in later chapters, so this chapter will notgo into a lot of detail except when discussing the timer interrupt.
17.4.1 The 8259A Programmable Interrupt Controller (PIC)
The 8259A (8259[6] or PIC, hereafter) programmableinterrupt controller chip accepts interrupts from up to eight differentdevices. If any one of the devices requests service, the 8259 will togglean interrupt output line (connected to the CPU) and pass a programmableinterrupt vector to the CPU. You can cascade the device to support up to64 devices by connecting nine 8259s together: eight of the devices witheight inputs each whose outputs become the eight inputs of the ninth device.A typical PC uses two of these devices to provide 15 interrupt inputs (sevenon the master PIC with the eight input coming from the slave PIC to processits eight inputs)[7]. The sections following thisone will describe the devices connected to each of those inputs, for nowwe will concentrate on what the 8259 does with those inputs. Nevertheless,for the sake of discussion, the following table lists the interrupt sourceson the PC:
The 8259 PIC is a very complex chip to program. Fortunately, all of thehard stuff has already been done for you by the BIOS when the system boots.We will not discuss how to initialize the 8259 in this text because thatinformation is only useful to those writing operating systems like Linux,Windows, or OS/2. If you want your interrupt service routines to run correctlyunder DOS or any other OS, you must not reinitialize the PIC.
The PICs interface to the system through four I/O locations: ports 20h/0A0hand 21h/0A1h. The first address in each pair is the address of the masterPIC (IRQ 0-7), the second address in each pair corresponds to the slavePIC (IRQ 8-15). Port 20h/0A0h is a read/write location to which you writePIC commands and read PIC status, we will refer to this as the command registeror the status register. The command register is write only, the status registeris read only. They just happen to share the same I/O location. The read/writelines on the PIC determine which register the CPU accesses. Port 21h/0A1his a read/write location that contains the interrupt mask register, we willrefer to this as the mask register. Choose the appropriate address dependingupon which interrupt controller you want to use.
The interrupt mask register is an eight bit register that lets you individuallyenable and disable interrupts from devices on the system. This is similarto the actions of the
cli and sti instructions,but on a device by device basis. Writing a zero to the corresponding bitenables that device's interrupts. Writing a one disables interrupts fromthe affected device. Note that this is non-intuitive. The figure below providesthe layout of the interrupt mask register.
When changing bits in the mask register, it is important that you notsimply loadal with a value and output it directly to the maskregister port. Instead, you should read the mask register and then logicallyorin or and out the bits you want to change;finally, you can write the output back to the mask register. The followingcode sequence enables COM1: interrupts without affecting any others:
in al, 21h ;Read existing bits. and al, 0efh ;Turn on IRQ 4 (COM1). out 21h, al ;Write result back to PIC.The command register provides lots of options, but there are only threecommands you would want to execute on this chip that are compatible withthe BIOS' initialization of the 8259: sending an end of interrupt commandand sending one of two read status register commands.
One a specific interrupt occurs, the 8259 masks all further interrupts fromthat device until is receives an end of interrupt signal from the interruptservice routine. On PCs running DOS, you accomplish this by writing thevalue 20h to the command register. The following code does this:
mov al, 20h out 20h, al ;Port 0A0h if IRQ 8-15.You must send exactly one end of interrupt command to the PIC for each interruptyou service. If you do not send the end of interrupt command, the PIC willnot honor any more interrupts from that device; if you send two or moreend of interrupt commands, there is the possibility that you will accidentallyacknowledge a new interrupt that may be pending and you will lose that interrupt.
For some interrupt service routines you write, your ISR will not be theonly ISR that an interrupt invokes. For example, the PC's BIOS providesan ISR for the timer interrupt that maintains the time of day. If you patchinto the timer interrupt, you will need to call the PC BIOS' timer ISR sothe system can properly maintain the time of day and handle other timingrelated chores (see"Chaining InterruptService Routines" on page 1010). However, the BIOS' timer ISR outputsthe end of interrupt command. Therefore, you should not output the end ofinterrupt command yourself, otherwise the BIOS will output a second endof interrupt command and you may lose an interrupt in the process.
The other two commands you can send the 8259 let you select whether to readthe in-service register (ISR) or the interrupt request register (IRR). Thein-service register contains set bits for each active ISR (because the 8259allows prioritized interrupts, it is quite possible that one ISR has beeninterrupted by a higher priority ISR). The interrupt request register containsset bits in corresponding positions for interrupts that have not yet beenserviced (probably because they are a lower priority interrupt than theinterrupt currently being serviced by the system). To read the in-serviceregister, you would execute the following statements:
; Read the in-service register in PIC #1 (at I/O address 20h) mov al, 0bh out 20h, al in al, 20hTo read the interrupt request register, you would use the following code:
; Read the interrupt request register in PIC #1 (at I/O address 20h) mov al, 0ah out 20h, al in al, 20hWriting any other values to the command port may cause your system to malfunction.
17.4.2 The Timer Interrupt (INT 8)
The PC's motherboard contains an 8254 compatible timer chip. This chipcontains three timer channels, one of which generates interrupts every 55msec (approximately). This is about once every 1/18.2 seconds. You willoften hear this interrupt referred to as the "eighteenth second clock."We will simply call it the timer interrupt.
The timer interrupt vector is probably the most commonly patched interruptin the system. It turns out there are two timer interrupt vectors in thesystem. Int 8 is the hardware vector associated with the timer interrupt(since it comes in on IRQ 0 on the PIC). Generally, you should not patchthis interrupt if you want to write a timer ISR. Instead, you should patchthe second timer interrupt, interrupt 1ch. The BIOS' timer interrupt handler(int 8) executes an
int 1ch instruction before it returns.This gives a user patched routine access to the timer interrupt. Unlessyou are willing to duplicate the BIOS and DOS timer code, you should nevercompletely replace the existing timer ISR with one of your own, you shouldalways ensure that the BIOS and DOS ISRs execute in addition to your ISR.Patching into the int 1ch vector is the easiest way to do this.Even replacing the int 1ch vector with a pointer to your ISR is very dangerous.The timer interrupt service routine is the one most commonly patched byvarious resident programs. By simply writing the address of your ISR intothe timer interrupt vector, you may disable such resident programs and causeyour system to malfunction. To solve this problem, you need to create aninterrupt chain. For more details, see the section"ChainingInterrupt Service Routines" on page 1010.
By default the timer interrupt is always enabled on the interrupt controllerchip. Indeed, disabling this interrupt may cause your system to crash orotherwise malfunction. At the very least, you system will not maintain thecorrect time if you disable the timer interrupt.
17.4.3 The Keyboard Interrupt (INT 9)
The keyboard microcontroller on the PC's motherboard generates two interruptson each keystroke - one when you press a key and one when you release it.This is on IRQ 1 on the master PIC. The BIOS responds to this interruptby reading the keyboard's scan code, converting this to an ASCII character,and storing the scan and ASCII codes away in the system type ahead buffer.
By default, this interrupt is always enabled. If you disable this interrupt,the system will not be able to respond to any keystrokes, including ctrl-alt-del.Therefore, your programs should always reenable this interrupt if they everdisable it.
17.4.4 The Serial Port Interrupts (INT 0Bh and INT 0Ch)
The PC uses two interrupts, IRQ 3 and IRQ 4, to support interrupt drivenserial communications. The 8250 (or compatible) serial communications controllerchip (SCC) generates an interrupt in one of four situations: a characterarriving over the serial line, the SCC finishes the transmission of a characterand is requesting another, an error occurs, or a status change occurs. TheSCC activates the same interrupt line (IRQ 3 or 4) for all four interruptsources. The interrupt service routine is responsible for determining theexact nature of the interrupt by interrogating the SCC.
By default, the system disables IRQ 3 and IRQ 4. If you install a serialISR, you will need to clear the interrupt mask bit in the 8259 PIC beforeit will respond to interrupts from the SCC. Furthermore, the SCC designincludes its own interrupt mask. You will need to enable the interrupt maskson the SCC chip as well. For more information on the SCC, see the appropriatechapter.
17.4.5 The Parallel Port Interrupts (INT 0Dh and INT 0Fh)
The parallel port interrupts are an enigma. IBM designed the originalsystem to allow two parallel port interrupts and then promptly designeda printer interface card that didn't support the use of interrupts. As aresult, almost no DOS based software today uses the parallel port interrupts(IRQ 5 and IRQ 7). Indeed, on the PS/2 systems IBM reserved IRQ5 which theyformerly used for LPT2:.
However, these interrupts have not gone to waste. Many devices which IBM'sengineers couldn't even conceive when designing the first PC have made gooduse of these interrupts. Examples include SCSI cards and sound cards. Manydevices today include "interrupt jumpers" that let you selectIRQ 5 or IRQ 7 when installing the device.
Since IRQ 5 and IRQ 7 find such little use as parallel port interrupts,we will effectively ignore the "parallel port interrupts" in thistext.
17.4.6 The Diskette and Hard Drive Interrupts (INT 0Eh and INT 76h)
The floppy and hard disk drives generate interrupts at the completionof a disk operation. This is a very useful feature for multitasking systemslike OS/2, Linux, or Windows. While the disk is reading or writing data,the CPU can go execute instructions for another process. When the disk finishesthe read or write operation, it interrupts the CPU so it can resume theoriginal task.
While managing the disk drives would be an interesting topic to cover inthis text, this book is already long enough. Therefore, this text will avoiddiscussing the disk drive interrupts (IRQ 6 and IRQ 14) in the interestof saving some space. There are many texts that cover low level disk I/Oin assembly language, see the bibliography for details.
By default, the floppy and hard disk interrupts are always enabled. Youshould not change this status if you intend to use the disk drives on yoursystem.
17.4.7 The Real-Time Clock Interrupt (INT 70h)
PC/AT and later machines included a CMOS real-time clock. This deviceis capable of generating timer interrupts in multiples of 976msec(let's call it 1 msec). By default, the real-time clock interrupt is disabled.You should only enable this interrupt if you have an int 70h ISR installed.
17.4.8 The FPU Interrupt (INT 75h)
The 80x87 FPU generates an interrupt whenever a floating point exceptionoccurs. On CPUs with built-in FPUs (80486DX and better) there is a bit inone of the control register you can set to simulate a vectored interrupt.BIOS generally initializes such bits for compatibility with existing systems.
By default, BIOS disables the FPU interrupt. Most programs that use theFPU explicitly test the FPU's status register to determine if an error occurs.If you want to allow FPU interrupts, you must enable the interrupts on the8259 and on the 80x87 FPU.
17.4.9 Nonmaskable Interrupts (INT 2)
The 80x86 chips actually provide two interrupt input pins. The firstis the maskable interrupt. This is the pin to which the 8259 PIC connects.This interrupt is maskable because you can enable or disable it with the
cli andsti instructions. The nonmaskable interrupt,as its name implies, cannot be disabled under software control. Generally,PCs use this interrupt to signal a memory parity error, although certainsystems use this interrupt for other purposes as well. Many older PC systemsconnect the FPU to this interrupt.This interrupt cannot be masked, so it is always enabled by default.
17.4.10 Other Interrupts
As mentioned in the section on the 8259 PIC, there are several interruptsreserved by IBM. Many systems use the reserved interrupts for the mouseor for other purposes. Since such interrupts are inherently system dependent,we will not describe them here.
[6] The original 8259 was designed for Intel's8080 system. The 8259A provided support for the 80x86 and some other features.Since almost no one uses 8259 chips anymore, this text will use the genericterm 8259.
[7] The original IBM PC and PC/XTmachines only supported eight interrupts via one 8259 chip. IBM, and virtuallyall clone manufacturers, added the second PIC in PC/AT and later designs.
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