MSI

从各处转载，算是原创吧。谢谢原作者。

From: 

http://blog.sina.com.cn/s/blog_6472c4cc0100qxc6.html

3.3.2 处理器到PCI处理器到PCI设备的数据传送

下文以图3‑2所示的处理器系统为例，说明处理器向PCI设备11进行存储器写的数据传送过程。处理器向PCI设备进行读过程与写过程略有区别，因为存储器写使用Posted方式，而存储器读使用Non-Posted方式，但是存储器读使用的地址译码方式与存储器写类似，因此本节对处理器向PCI设备进行存储器读的过程不做进一步介绍。

PCI设备11在PCI总线域的地址范围是0x7300-0000~0x73FF-FFFF。这段空间在存储器域中对应的地址范围是0xF300-0000~0xF3FF-FFFF。下文我们假设处理器使用存储器写指令，访问0xF300-0008这个存储器地址，其步骤如下。

(1)      存储器域将0xF300-0008这个地址发向HOST主桥，0xF000-0000~0xF7FF-FFFF这段地址已经由HOST主桥映射到PCI总线域地址空间，所以HOST主桥认为这是一个对PCI设备的访问。因此HOST主桥将首先接管这个存储器写请求。

(2)      HOST主桥将存储器域的地址0xF300-0008转换为PCI总线域的地址0x7300-0008，并通过总线仲裁获得PCI总线0的使用权，启动PCI存储器写周期，并将这个存储器写总线事务发送到PCI总线0上。值得注意的是，这个存储器读写总线事务使用的地址为0x7300-0008，而不是0xF300-0008。

(3)      PCI总线0的PCI桥1发现0x7300-0008在自己管理的地址范围内，于是接管这个存储器写请求，并通过总线仲裁逻辑获得PCI总线1的使用权，并将这个请求转发到PCI总线1上。

(4)      PCI总线1的PCI设备11发现0x7300-0008在自己的BAR0寄存器中命中，于是接收这个PCI写请求，并完成存储器写总线事务。

6.2 PowerPC处理器如何处理MSI中断请求

 

使用MPIC中断控制器处理MSI中断时，PCIe设备的MSI报文，其目的地址为MPIC中断控制器的MSIIR寄存器。当该寄存器被PCIe设备写入后，MPIC中断控制器将向处理器内核提交中断请求，之后处理器再通过读取MPIC中断控制器的ACK寄存器获得中断向量号，并进行相应的中断处理。这种方式与x86处理器的FSB Interrupt Message机制相比，处理器需要读取ACK寄存器，从而中断处理的延时较大。

目前Freescale的P4080处理器对MPIC中断控制器进行了优化。在P4080处理器中，MPIC中断控制器向处理器提交中断请求的同时，也向处理器内核提交中断向量，处理器内核不必读取ACK寄存器获得中断向量，从而缩短了中断处理延时。使用这种方法的效率与x86处理器使用的FSB Interrupt Message机制相当。

详细参见：

http://blog.sina.com.cn/s/blog_6472c4cc0102dskk.html

6.3 x86处理器如何处理MSI-X中断请求

 

在x86处理器系统中，PCIe设备使用的Message Address字段仍然保存PCI总线域的地址，其格式如图6‑7所示。

其中第31~20位，存放FSB Interrupts存储器空间的基地址，其值为0xFEE。当PCIe设备对0xFEEX-XXXX这段“PCI总线域”的地址空间进行写操作时，MCH/ICH将会首先进行“PCI总线域”到“存储器域”的地址转换，之后将这个写操作翻译为FSB总线的Interrupt Message总线事务，从而向CPU内核提交中断请求。

From:  http://blog.sina.com.cn/s/blog_6472c4cc0102dskl.html

3. What is MSI/MSI-X?
Message Signaled Interrupt (MSI), as described in the PCI Local Bus Specification Revision 2.3 or latest, is an optional feature, and a required feature for PCI Express devices. MSI enables a device function to request service by sending an Inbound Memory Write on its PCI bus to the FSB as a Message Signal Interrupt transaction. Because MSI is generated in theform of a Memory Write, all transaction conditions, such as a Retry, Master-Abort, Target-Abort or normal completion, are supported.

4: FSB, ICH, MCH

5:  what is Intel front side bus interrupt transaction

From: 

http://techreport.com/forums/viewtopic.php?f=2&t=73117

Glorious Darth Gerbil

APIC is what modern computers used to handle interrupts. Everything you mentioned are just links on a chain. Let's do a diagram.

PCIe Device -> MSI -> ACPI -> FSB -> LINT[1:0] -> CPU

A device on a PCI wants to do an interrupt. Under PCIe, there are no hardware interrupt pins. What happens is that the device writes out a message to a special memory address (This is MSI). This message contains the IDT vector and relevant info. The APIC reads this address, figures out what to do according to its tables, and then loads the IDT vector into a memory location and then asserts one of those pins across the FSB. The CPU is reading those two pins, and when it sees the pin assertion it reads that memory location, uses the vector to find the right entry in the IDT, uses that address to run the ISR and away we go.

There is a way to use the LINT[1:0] as the old school straight INTR and NMI, but that's backwards compatibility stuff.

logicman112 Gerbil In Training

Thank you for the replies. Particularly Glorious.
Glorious, i have copied some lines of 82945 data sheet (north bridge which is connected to Core 2 Duo or Core Duo):

---------------------------------------------------------------------------------------------------------
10.1.6
FSB Interrupt Overview
The Intel Core Duo and Intel Core Solo processor supports FSB interrupt delivery. They
do not support the APIC serial bus interrupt delivery mechanism. Interrupt related
messages are encoded on the FSB as “Interrupt Message Transactions”. FSB interrupts
may originate from the CPUs on the FSB, or from a downstream device on the DMI or
PCI Express Graphics Attach. In the later case, the (G)MCH drives the “Interrupt
Message Transaction” on the FSB.
In the IOxAPIC environment, an interrupt is generated from the IOxAPIC to a CPU in
the form of an upstream Memory Write. The ICH contains IOxAPICs, and its interrupts
are generated as upstream DMI Memory Writes. Furthermore, the PCI Local Bus
Specification and PCI Express* Base Specification define MSI’s (Message Signaled
Interrupts) that are also in the form of Memory Writes. A PCI device may generate an
interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the
IOxAPIC. The MSI may be directed to the IOxAPIC. The IOxAPIC in turn generates an
interrupt as an upstream DMI Memory Write. Alternatively, the MSI may directly route
to the FSB. The target of an MSI is dependent on the address of the interrupt Memory
Write. The (G)MCH forwards upstream DMI and PCI Express Graphics Attach low
priority Memory Writes to address 0FEEx_xxxxh to the FSB as “Interrupt Message
Transactions”.
---------------------------------------------------------------------------------------------------------

Do you think MSI (message signalled interrupt) is done by CPU's APIC and the pins, LINT[1::0]? or interrupt is delivered as a message by data bus of the CPU or REQ pins(CPU request pins which specify the type of FSB transaction) ?

Glorious Darth Gerbil :

I don't think you're understanding what I'm telling you. It's delivered as message on one bus, and as an interrupt on another. For MSI, it's an in-band message. For the FSB, it's an side-band interrupt on the LINT[0:1] pins. Remember, these are all links on a chain.

What that data sheet is telling you is that interrupts go over the FSB. This is relevant information because back in the day (prior to the P4, I believe), the APIC had a different, direct, 3 line serial bus to the CPU. 

The Datasheet also talks about yet another link, the link between the southbridge (ICH) and northbridge (MCH), in the chipset. That's the DMI. But you don't really need to worry about that. 

And, of course, QPI completely changes all of this again, so that it's a in-band message all the way to the CPU.