ML507的配置

1、配置方法：

（1）通过jtag下载程序到FPGA，（使用CPU Rst来使程序运行）或者程序自动复位并运行。

（2）通过jtag下载程序到Platform Flash Memory、Linear Flash Memory、SPI Flash Memory中，选择好Mode DIP Switches，使用Prog来配置程序并运行。

（3）通过jtag下载程序到flash卡，通过System ACE，使用ACE Rst来使程序运行。

2、Mode DIP Switches的配置

Switch(SW3) Function

1 Config Address [2].

2 Config Address [1].

3 Config Address [0].

4 MODE [2].

5 MODE [1].

6 MODE [0].

7 Platform Flash Fallback (On = Enable, Off= Disable).(1)

8 System ACE Configuration (On = Enable,Off = Disable). When enabled,the System ACE controller configures the FPGA fromthe CF card whenever a card is inserted or the SYSACE RESET button is pressed.

 

Mode[2:0]Mode

000 Master Serial (Platform Flash, up tofour configurations)

001 SPI (One configuration)

010 BPI Up (Parallel NOR Flash, up to fourconfigurations)

011 BPI Down (Parallel NOR Flash, up tofour configurations)

100 Master SelectMAP (Platform Flash, up tofour configurations)

101 JTAG (PC4, System ACE up to eightconfigurations)

110 Slave SelectMAP (Platform Flash, up tofour configurations)

111 Slave Serial (Platform Flash, up tofour configurations)

 

Configuration Address [2:0] allows the userto select among multiple configuration

images. For System ACE configuration, up toeight possible configurations can be stored

on a CF card. Platform Flash and LinearFlash can hold up to four separate bitstreams that

can be chosen by Configuration Address[2:0].

3、

在Boundary Scan时，一片Platform Flash Prom只能被扫描出一片，ML507上有两片Platform Flash Prom。

4、下载过程：

（1）先生成.mcf 文件，在选择下载的选项，在选择相关的DIP并按一下prog来启动FPGA

（2）注意：ug347里面所说的Slave 和Master是指FPGA，而IMPACT里面设置的是Prom是Slave 或者是Master。正好和表中相反。

（3）技术支持的回复（Slave Parrlell）

1. assign mcs file to the first device(xcf32p) in JTAG chain.

2. Check these options of PROM whenprogramming

   -Parallel mode (checked)

   -Prom is Slave (checked)

3. Then program MCS file to PROM.

4. Check DIP's option

   -bit0 to bit8 should be 000 100 00

5. Presh PROG_B button.

（4）做一个实验：Slave SelectMAP：00011000。对了，呵呵。

5、两片xc32p的用途

技术支持的回答：

If bit stream's size is larger than thedensity of PROM, 2 PROMs will be cascated to program FPGA. There is an orderabout how 2 PROMs send data. PROM whose CE pin is controlled by FPGA is thefirst one sending data. After all data in this PROM is sent out, the secondPROM whose CE pin is controlled by the first PROM sends out the data. In youboard, the bit stream's size does not exceed 32M bits so one PROM is used. Andone first PROM in JTAG chain should be used.