cy7c68013a笔记

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SCL,SDA: 未连接 I2C 器件，必须上拉到 3.3V; 连接配置芯片（PID,VID）

PA2/SLOE: FIFO输出使能

PA4/FIFOADR0:FIFO ADR

PA6/PKTEND:FIFO小于包大小时使用

PA7/FLAGD /SLCS: 片选

RDY0 /SLRD：读，同步读：fifo指针随IFCLK上升时递增；异步读：fifo指针随SLRD上升沿时递增

RDY1 /SLWR：写

固件，keil 程序

void TD_Init(void)             // Called once at startup
{
    // set the CPU clock to 48MHz
    CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
    SYNCDELAY;
    IFCONFIG =0x43;// IFCFG1:0 = 11, the Slave FIFO    in synchronous mode (IFCONFIG.3 = 0)

   SYNCDELAY;
   EP2CFG=0xA0;//10:valid, out, 10:bulk,   bit3,0:512 byte, 1:1024 byte
   SYNCDELAY;
   EP4CFG=0; //0
   SYNCDELAY;
   EP6CFG=0xE0;//11:valid, in, 10:bulk,   bit3,0:512 byte, 1:1024 byte
   SYNCDELAY;
   EP8CFG=0;

   SYNCDELAY;
   FIFORESET = 0x80;
   SYNCDELAY;
   FIFORESET = 0x02;
   SYNCDELAY;
    FIFORESET = 0x04;
   SYNCDELAY;
   FIFORESET = 0x06;
   SYNCDELAY;
   FIFORESET = 0x08;
   SYNCDELAY;
   FIFORESET = 0x00;
   SYNCDELAY;
   PINFLAGSAB = 0x8C; //8:FLAGB ,EP2 EF , C:FLAGA, EP2 FF
   SYNCDELAY;
   PINFLAGSCD = 0xFE; //F:FLAGD ,EP8 FF , E:FLAGC, EP6 FF
   SYNCDELAY;
   PORTACFG   = 0x0;
   SYNCDELAY;
   FIFOPINPOLAR = 0x00; //0: active low
   SYNCDELAY;
   EP2FIFOCFG = 0x11;    //auto out, wordwide
   SYNCDELAY;
   EP6FIFOCFG = 0x09;    //auto in, wordwide
   SYNCDELAY;
}

cypress的烧写工具：control center

altera的file---》convert programming file

选择programming file type:JTAG indirect Configuration File(.jic)

选择 Flash Leader: EP4CE10

SOF Data: 程序名.sof