verilog语言设计有限状态机习题

module seqdet(x,z,clk,rst,state);

input x,clk,rst;

output z;

output[2:0] state;

reg[2:0] state;

wire z;

parameter IDLE='d0, A='d1, B='d2,

C='d3, D='d4,

E='d5;

assign z = ( state==D)? 1 : 0; //?x=0???????E?

//???D??x??1???

//???1????? state==E && x==0 ??

always @(posedge clk)

if(!rst)

begin

state <= IDLE;

end

else

casex(state)

IDLE : if(x==1)

begin

state <= A;

end

A:if(x==1)

begin

state <= B;

end

else

begin

state <= E;

end

B: if(x==1)

begin

state <= C;

end

else

begin

state <= E;

end

C: if(x==1)

begin

state <= D;

end

else

begin

state <= E;

end

D: if(x==0)

begin

state <= E;

end

E: if(x==1)

begin

state <= A;

end

if(x==0)

begin

state <=E;

end

default:state=IDLE; //??????????

endcase

endmodule

 

 

 

 

测试程序

`timescale 1ns/1ns

`include "ztj.v"

module seqdet_Top;

reg clk,rst;

reg[23:0] data;

wire[2:0] state;

wire z,x;

assign x=data[23];

always #10 clk = ~clk;

always @(posedge clk)

data={data[22:0],data[23]};

initial

 

begin

clk=0;

rst=1;

#2 rst=0;

#30 rst=1;

data ='b1111_0111_1110_1111;

//#500 $stop;

end

seqdet m(x,z,clk,rst,state);

endmodule