CR0-4寄存器介绍

CR0

x86_32的CR0为32bit。X86_64下为64bit，其中低32bit与x86_32的CR0保持一致，高32bit没有定义，作保留使用，除了bit4其他所有位都是可读可写的。

Protected-Mode Enable (PE)Bit. Bit 0. PE=0,表示CPU处于实模式; PE=1表CPU处于保护模式，并使用分段机制。

Paging Enable (PG) Bit. Bit31. 该位控制分页机制，PG=1，启动分页机制；PG=0,不使用分页机制。

CR2

存放发生页错误时的虚拟地址，格式如下：

CR3

用来存放最高级页目录地址(物理地址），各级页表项中存放的也是物理地址。格式如下：

Page-Level Writethrough (PWT) Bit. Bit 3. Page-levelwritethrough indicates whether the highest-

level page-translation table has a writeback or writethroughcaching policy. When PWT=0, the table

has a writeback caching policy. When PWT=1, the table has awritethrough caching policy.

Page-Level Cache Disable (PCD) Bit. Bit 4.PCD=1,表示最高目录表不可缓存，PCD=0,相反。

   图3-4中不使用PAE技术，有两层页表。最高层为页目录有1024项，占用4KB。page_directory_table baseaddress为物理地址，指向4KB对齐的页目录地址。

   图3-5中，使用PAE技术，三层页表寻址。最高层为页目录指针，4项，占用32B空间。所以 page_directory_table baseaddress为27位，指向32B对齐的页目录指针表。

CR4

  legacy mode 下低32位与x86_32的CR4一致，

Virtual-8086 Mode Extensions (VME) Bit. Bit 0. SettingVME to 1 enables hardware-supported

performance enhancements for software running in virtual-8086mode. Clearing VME to 0 disables

this support. The enhancements enabled when VME=1include:

Virtualized, maskable, external-interrupt control andnotification using the VIF and VIP bits in the

rFLAGS register. Virtualizing affects the operation of severalinstructions that manipulate the

rFLAGS.IF bit.

Selective intercept of software interrupts (INTn instructions)using the interrupt-redirection

bitmap in the TSS.

Protected-Mode Virtual Interrupts (PVI) Bit. Bit 1.Setting PVI to 1 enables support for protected-

mode virtual interrupts. Clearing PVI to 0 disables thissupport. When PVI=1, hardware support of

two bits in the rFLAGS register, VIF and VIP, isenabled.

Only the STI and CLI instructions are affected by enablingPVI. Unlike the case when CR0.VME=1,

the interrupt-redirection bitmap in the TSS cannot be used forselective INTn interception.

PVI enhancements are also supported in long mode. See “VirtualInterrupts” on page 251 for more

information on using PVI.

Time-Stamp Disable (TSD) Bit. Bit 2. The TSD bit allowssoftware to control the privilege level at

which the time-stamp counter can be read. When TSD is clearedto 0, software running at any privilege

level can read the time-stamp counter using the RDTSC orRDTSCP instructions. When TSD is set to

1, only software running at privilege-level 0 can execute theRDTSC or RDTSCP instructions.

Debugging Extensions (DE) Bit. Bit 3. Setting the DEbit to 1 enables the I/O breakpoint capability

and enforces treatment of the DR4 and DR5 registers asreserved. Software that accesses DR4 or DR5

when DE=1 causes a invalid opcode exception (#UD).

When the DE bit is cleared to 0, I/O breakpoint capabilitiesare disabled. Software references to the

DR4 and DR5 registers are aliased to the DR6 and DR7registers, respectively.

Page-Size Extensions (PSE) Bit. Bit 4.PSE=1,启用PSE，PSE=0，不启用。

Physical-Address Extension (PAE) Bit. Bit5.PAE=1,启用PAE，支持2MB的超级页（superpage）；PAE=0,不启用PAE。

Machine-Check Enable (MCE) Bit. Bit 6. Setting MCE to 1enables the machine-check exception

mechanism. Clearing this bit to 0 disables the mechanism. Whenenabled, a machine-check exception

(#MC) occurs when an uncorrectable machine-check error isencountered.

Regardless of whether machine-check exceptions are enabled,the processor records enabled-errors

when they occur. Error-reporting is performed by themachine-check error-reporting register banks.

Each bank includes a control register for enabling errorreporting and a status register for capturing

errors. Correctable machine-check errors are also reported,but they do not cause a machine-check

exception.

See Chapter 9, “Machine Check Mechanism,” for a description ofthe machine-check mechanism, the

registers used, and the types of errors captured by themechanism.

Page-Global Enable (PGE) Bit. Bit 7. When pagetranslation is enabled, system-software

performance can often be improved by making some pagetranslations global to all tasks and

procedures. Setting PGE to 1 enables the global-pagemechanism. Clearing this bit to 0 disables the

mechanism.

When PGE is enabled, system software can set the global-page(G) bit in the lowest level of the pagetranslation hierarchy to 1,indicating that the page translation is global. Page translationsmarked asglobal are not invalidated in the TLB when thepage-translation-table base address (CR3) is updated.

When the G bit is cleared, the page translation is not global.All supported physical-page sizes also support theglobal-page mechanism. See “Global Pages” on page 142 forinformation on using the global-pagemechanism.

Performance-Monitoring Counter Enable (PCE) Bit. Bit 8.Setting PCE to 1 allows software running at anyprivilege level to use the RDPMC instruction. Software uses theRDPMC instruction to read theperformance-monitoring MSRs, PerfCtrn. Clearing PCE to 0 allowsonly the most-privileged software (CPL=0) to usethe RDPMC instruction.

FXSAVE/FXRSTOR Support (OSFXSR) Bit. Bit 9. Systemsoftware must set the OSFXSR bit to 1 to enableuse of the 256-bit and 128-bit media instructions. When this bit isset to 1, it also indicates

that system software uses the FXSAVE and FXRSTOR instructionsto save and restore the processor

state for the x87, 64-bit media, and 128-bit mediainstructions.

Clearing the OSFXSR bit to 0 indicates that 256-bit and128-bit media instructions cannot be used.

Attempts to use those instructions while this bit is clearresult in an invalid-opcode exception (#UD).

Software can continue to use the FXSAVE/FXRSTOR instructionsfor saving and restoring the processor state forthe x87 and 64-bit media instructions.

Unmasked Exception Support (OSXMMEXCPT) Bit. Bit 10.System software must set the OSXMMEXCPT bit to 1when it supports the SIMD floating-point exception (#XF) forhandling of unmasked 256-bit and 128-bit mediafloating-point errors. Clearing the OSXMMEXCPT bit to0 indicates the #XF handler is not supported. WhenOSXMMEXCPT=0, unmasked 128-bitmedia floating-point exceptions cause aninvalid-opcode exception (#UD). See “SIMDFloating-Point Exception Causes” in Volume 1 formore information on unmasked SSE floating-point exceptions.

XSAVE and Extended States (OSXSAVE) Bit. Bit 18. Ifthis bit is set to 1 then the operating system

supports the XGETBV, XSETBV, XSAVE and XRSTOR instructions.The processor will also be able

to execute XGETBV and XSETBV instructions in order to read andwrite XCR0. Also, if set, the

XSAVE and XRSTOR instructions can save and restore the x87 FPUstate (including MMX registers),

the SSE state (YMM/XMM registers and MXCSR), along with otherprocessor extended states

enabled in XCR0.

Extended Feature Enable Register(EFER)

System-Call Extension (SCE) Bit. Bit 0. Setting thisbit to 1 enables the SYSCALL and SYSRET

instructions. Application software can use these instructionsfor low-latency system calls and returns in anon-segmented (flat) address space. See “Fast System Call andReturn” on page 152 foradditional information.

Long Mode Enable (LME) Bit. Bit 8. LME=1,启用longmode，注意必须先将CR0.PG=0后才能设置LME=1,然后再设置CR0.PG=1，则进入long mode。LME=0，使用legacy mode。

Long Mode Active (LMA) Bit. Bit 10, read-only. This bitindicates that long mode is active. The

processor sets LMA to 1 when both long mode and paging havebeen enabled by system software. See

Chapter 14, “Processor Initialization and Long ModeActivation,” for more information onactivating long mode.

When LMA=1, the processor is running either in compatibilitymode or 64-bit mode, depending on the

value of the L bit in a code-segment descriptor, as shown inFigure 1-6 on page 12.

When LMA=0, the processor is running in legacy mode. In thismode, the processor behaves like a

standard 32-bit x86 processor, with none of the new 64-bitfeatures enabled.

No-Execute Enable (NXE) Bit. Bit 11. Setting this bit to 1enables the no-execute page-protection

feature. The feature is disabled when this bit is cleared to0. See “No Execute (NX) Bit” on page 145 for moreinformation.

Before setting NXE, system software should verify theprocessor supports the feature by examining

the extended-feature flags returned by the CPUID instruction.For more information, see the CPUID

Specification, order# 25481.

Secure Virtual Machine Enable (SVME) Bit. Bit 12. Enables theSVM extensions. When this bit is

zero, the SVM instructions cause #UD exceptions. EFER.SVMEdefaults to a reset value of zero. The

effect of turning off EFER.SVME while a guest is running isundefined; therefore, the VMM should

always prevent guests from writing EFER. SVM extensions can bedisabled  by setting VM_CR.SVME_DISABLE .  For moreinformation, see descriptions of LOCK andSMVE_DISABLE bits in Section 15.29.1, “VM_CR MSR(C001_0114h),” on page 431.

Long Mode Segment Limit Enable (LMSLE) bit. Bit 13. Settingthis bit to 1 enables certain limit

checks in 64-bit mode. See Section 4.12.2, "Data Limit Checksin 64-bit Mode", for more information

on these limit checks.

Fast FXSAVE/FXRSTOR (FFXSR) Bit. Bit 14. Setting this bit to 1enables the FXSAVE and FXRSTOR instructions toexecute faster in 64-bit mode at CPL 0. This is accomplished by notsaving or restoring the XMM registers(XMM0-XMM15). The FFXSR bit has no effect whenthe FXSAVE/FXRSTOR instructions are executed innon 64-bit mode, or when CPL > 0. The FFXSRbit does not affect the save/restore of the legacyx87 floating-point state, or the save/restore of MXCSR.

Before setting FFXSR, system software should verify whetherthis feature is supported by examining

the CPUID extended feature flags returned by the CPUIDinstruction. For more information, see

"Function 8000_0001h: Processor Signature and AMD Features" inVolume 3.