GMII、RGMII、SGMII

Gigabit Media Independent Interface[edit]

Gigabit Media Independent Interface (GMII) is an interface between the Media Access Control (MAC) device and the physical layer (PHY). The interface defines speeds up to 1000 Mbit/s, implemented using an eight-bit data interface clocked at 125 MHz, and is backwards compatible with the Media Independent Interface (MII) specification. It can also operate on fall-back speeds of 10 or 100 Mbit/s as per the MII specification.

Data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check (CRC).

The GMII interface is defined in IEEE Standard 802.3, 2000 Edition.^[5]

Transmitter signals[edit]

• GTXCLK - clock signal for gigabit TX.. signals (125 MHz)
• TXCLK - clock signal for 10/100 Mbit signals
• TXD[7..0] - data to be transmitted
• TXEN - transmitter enable
• TXER - transmitter error (used to corrupt a packet)

There are two clocks, depending on whether the PHY is operating at gigabit or 10/100 Mb speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. Otherwise for 10 or 100 Mbit/s the TXCLK (supplied by PHY) is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent.

Receiver signals[edit]

• RXCLK - received clock signal (recovered from incoming received data)
• RXD[7..0] - received data
• RXDV - signifies data received is valid
• RXER - signifies data received has errors
• COL - Collision Detect (half-duplex connections only)
• CS - Carrier Sense (half-duplex connections only)

Management signals[edit]

• MDC - Management interface clock
• MDIO - Management interface I/O bidirectional pin.

The management interface controls the behaviour of the PHY. There are 32 addresses, each containing 16 bits. The first 16 addresses have a defined usage,^[6] while the others are device specific. These registers can be used to configure the device (say "only gigabit, full duplex", or "only full duplex") or can be used to determine the current operating mode.

Reduced Gigabit Media Independent Interface[edit]

Reduced Gigabit Media Independent Interface (RGMII) specifies a particular interface between an Ethernet MAC and PHY.

RGMII uses half the number of data pins as used in the GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock in 1000 Mbit/s operation, and by eliminating non-essential signals (carrier-sense and collision-indication). Thus RGMII consists only of: RX_CTL, RXC, RXD[3:0], TX_CTL, TXC, TXD[3:0] (12 pins, as opposed to GMII's 24).

Unlike GMII, the transmit clock signal is always provided by the MAC on the TXC line, rather than being provided by the PHY for 10/100 Mbit/s operation and by the MAC at 1000 Mbit/s.

In RGMII mode, TXD[3:0] are used as TD[3:0], TXD[3:0] run at double data rate with bits [3:0] presented on the rising edge of GTX_CLK, and bits [7:4] presented on the falling edge of GTX_CLK. In this mode, TXD[7:4] are ignored.

In RGMII 10/100BASE-T modes, the transmit data nibble is presented on TXD[3:0] on the rising edge of GTX_CLK.

RGMII supports Ethernet speeds of:

[Mbit/s][MHz]Bits/Clockcycle102.5410025 41000125 8

Serial Gigabit Media Independent Interface[edit]

The Serial Gigabit Media Independent Interface (SGMII) is a variant of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. It is used for Gigabit Ethernet but can also carry 10/100 MBit Ethernet.

It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin count serial 8B/10B coded interface (commonly referred to as a SerDes). Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (Clock recovery may be used alternatively). 10/100 MBit Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.

TheS_IN+/S_IN- signals are the Transmit Data. 1.25 GBaud input - Positive and Negative. Input impedance on the S_IN+/- signals may be programmed for 50 ohm or 75 ohm impedance by setting register 26.6. The input impedance default setting is determined by the 75/50 OHM configure signal.

Management Interface and Interrupt

The MDC signal is the management data clock reference for the serial management interface. A continuous clock stream is NOT expected. The maximum frequency supported is 8.3 MHz.

The MDIO signal is the management data. MDIO transfers management data in and out of the device synchronously to MDC. This signal requires a pull-up resistor in a range from 1.5 kohm to 10 kohm.

TheINTn signal: The polarity of the INTn signal may be programmed at hardware reset by setting the INT_POL bit. Polarity: 0 = Active High, 1 = Active Low.