学习笔记-Semihosting

如何理解Semihosting?（老帖重发，写得比较久了）

  Semihosting，顾名思义，就是"半主控"，意思就是说，运行在target board上的程序利用主机上的facilities的一种程序调试方式，主要是debug目标板时，利用主机的输入输出设备，例如在AxD的console上打印相应的调试信息或者用主机的键盘输入相应字符作为target上的程序的输入。
  C/C++ code默认是可以使用console的，例如，如果只包含C/C++的程序采用ARMulater模拟，就可以直接使用console作为程序的输出设备；如果程序包含有汇编代码，要使用主机设备的话，必须采用semihosting SWI方式。Semihosing SWI(以下简称SHS)，必须有相应的debug agent的支持，才能截获SHS，并向software debugger(AxD)请求相应的服务，如打印字符或者接受字符输入，这样的agents包括:
 1)ARMulater
 2)debug monitor（Angel）
 3)MultiICE
  由于调试裸板或者没有Angel可以供目标板使用的时候，主要还是要借助仿真器进行调试，所以第三种方式最为常用，下面主要就这种方式进行介绍。当然，UART也是一种最常用的调试接口，但是，使用Semihosting，可以独立地调试各个硬件模块的逻辑功能，确保各段代码正确后再进行集成，相应地省去了每次都要配置UART和另开一个hyperterminal观察调试信息。所以，我在开发的时候倾向于使用semihosting来调试相关的代码，这些代码使用C或者C++编写，也就是说和硬件配置关系不大。

=================================Below from ADS help===============================
Multi-ICE
When using Multi-ICE in default configuration, semihosting is implemented as follows:
1. On ARM7 processors:
 a) A breakpoint is set on the SWI vector.
 b) When this breakpoint is hit, Multi-ICE examines the SWI number.
 c) If the SWI is recognized as a semihosting SWI, Multi-ICE emulates it and transparently restarts execution of the application. 
 If the SWI is not recognized as a semihosting SWI, Multi-ICE halts the processor and reports an error.
2. On other processors:
 a) Vector-catch logic traps SWIs.
 b) If the SWI is recognized as a semihosting SWI, Multi-ICE emulates it and transparently restarts execution of the application. 
 If the SWI is not recognized as a semihosting SWI, Multi-ICE halts the processor and reports an error.
 This semihosting mechanism can be disabled or changed by the following debugger internal variables:
  $semihosting_enabled
 Set this variable to 0 to disable semihosting. If you are debugging an application running from ROM, this allows you to use an  additional watchpoint unit.
 Set this variable to 1 to enable semihosting. This is the default.
 Set this variable to 2 to enable Debug Communications Channel semihosting.
 The S bit in $vector_catch has no effect unless semihosting is disabled.
 $semihosting_vector
This variable controls the location of the breakpoint set by Multi-ICE to detect a semihosted SWI. It is set to the SWI entry in the exception vector table (0x8) by default.
If your application requires semihosting as well as having its own SWI handler, set $semihosting_vector to an address in your SWI handler. This address must point to an instruction that is only executed if your SWI handler has identified a call to a semihosting SWI. All registers must already have been restored to whatever values they had on entry to your SWI handler.
Multi-ICE handles the semihosted SWI and then examines the contents of lr and returns to the instruction following the SWI instruction in your code. 
Regardless of the value of $vector_catch, all exceptions and interrupts are trapped and reported as an error condition.
For details of how to modify debugger internal variables, see the appropriate debugger documentation.

 

最后一次修改2006.3.14

转自：http://blog.csdn.net/zhtek/article/details/723869