linux 下spi的使用 ，cc2500模块驱动

 static int __devinit cc2500_probe(struct spi_device *spi){

     spi->mode = SPI_MODE_0 ;//同时可以设置cs脚是高有效（或上SPI_CS_HIGH）还是低有效，默认低有效

<span style="font-family: Arial, Helvetica, sans-serif;"></span><span style="font-family: Arial, Helvetica, sans-serif;">spi_setup(spi);</span>

}

读写函数：

static int spi_rw(struct spi_device *spi, char *buf, size_t len){
struct spi_transfer t= {
.tx_buf=(const void*) buf,
.rx_buf=buf,
.len=len,
.cs_change=0,
.delay_usecs=150,
};
struct spi_message m;
spi_message_init(&m);
spi_message_add_tail(&t,&m);
if (spi_sync(spi, &m) != 0 || m.status != 0){
printk("Err : spi read/write error m.status:%d \n",m.status);
return -1;
}
return len - m.actual_length;
}

// 读一个寄存器时siez一定至少是2，因为长度为1时，时钟信号只会维持一个byte的时间，传输了地址后clk就消失了。

static char spi_read_reg(char reg){
char buf[2];
buf[0]=reg|0x80;
buf[1]=0xff;
spi_rw(cc2500->spi,buf,2);
//printk("buf0:%x buf1:%x \n",buf[0],buf[1]);
return buf[1];
}

static int spi_write_reg(char reg, char value){
char buf[2];
buf[0]=reg;
buf[1]=value;
int ret= spi_rw(cc2500->spi,buf,2);
printk("buf0:%x buf1:%x \n",buf[0],buf[1]);
return ret;
}

config(){

spi_write_reg(0x30,   0); //reset device 
spi_write_reg(TI_CCxxx0_IOCFG2,   0x06); // GDO2 output pin config.
spi_write_reg(TI_CCxxx0_IOCFG0,   0x0B); // GDO0 output pin config.
spi_write_reg(TI_CCxxx0_PKTLEN,   61); // Packet length.
spi_write_reg(TI_CCxxx0_PKTCTRL1, 0x07); // Packet automation control.
spi_write_reg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
spi_write_reg(TI_CCxxx0_PATABLE, 0xfe); // ?????????????????????????.
spi_write_reg(TI_CCxxx0_ADDR,     0x21); // Device address.
spi_write_reg(TI_CCxxx0_FIFOTHR,  0x0f); // Device address.
spi_write_reg(TI_CCxxx0_CHANNR,   0x00); // Channel number.
spi_write_reg(TI_CCxxx0_FSCTRL1,  0x06); // Freq synthesizer control.
spi_write_reg(TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
spi_write_reg(TI_CCxxx0_FREQ2,    0x5d); // Freq control word, high byte
spi_write_reg(TI_CCxxx0_FREQ1,    0x44); // Freq control word, mid byte.
spi_write_reg(TI_CCxxx0_FREQ0,    0xec); // Freq control word, low byte.
spi_write_reg(TI_CCxxx0_MDMCFG4,  0x78); // Modem configuration.
spi_write_reg(TI_CCxxx0_MDMCFG3,  0x93); // Modem configuration.
spi_write_reg(TI_CCxxx0_MDMCFG2,  0x03); // Modem configuration.
spi_write_reg(TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
spi_write_reg(TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
spi_write_reg(TI_CCxxx0_DEVIATN,  0x44); // Modem dev (when FSK mod en)
spi_write_reg(TI_CCxxx0_MCSM1 ,   0x00); //MainRadio Cntrl State Machine
spi_write_reg(TI_CCxxx0_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
spi_write_reg(TI_CCxxx0_FOCCFG,   0x16); // Freq Offset Compense. Config
spi_write_reg(TI_CCxxx0_BSCFG,    0x6C); //  Bit synchronization config.
spi_write_reg(TI_CCxxx0_AGCCTRL2, 0x43); // AGC control.
spi_write_reg(TI_CCxxx0_AGCCTRL1, 0x40); // AGC control.
spi_write_reg(TI_CCxxx0_AGCCTRL0, 0x91); // AGC control.
spi_write_reg(TI_CCxxx0_FREND1,   0x56); // Front end RX configuration.
spi_write_reg(TI_CCxxx0_FREND0,   0x10); // Front end RX configuration.
spi_write_reg(TI_CCxxx0_FSCAL3,   0xA9); // Frequency synthesizer cal.
spi_write_reg(TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
spi_write_reg(TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
spi_write_reg(TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
spi_write_reg(TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
spi_write_reg(TI_CCxxx0_TEST2,    0x88); // Various test settings.
spi_write_reg(TI_CCxxx0_TEST1,    0x31); // Various test settings.
spi_write_reg(TI_CCxxx0_TEST0,    0x0B); // Various test settings.

}

spi_write_reg(TI_CCxxx0_IOCFG2,   0x06); // GDO2 output pin config.

收到数据后GDO2电平会有变化，方便用中断

spi_write_reg(TI_CCxxx0_ADDR,     0x21); // Device address.

static size_t cc2500_send_function(){
char txBuf[255];
txBuf[0]=10; // packet length
int i =0;
txBuf[1]=0x21; // packet address 和上面配置的address要一致
for(i =0;i< 250;i++)
txBuf[i+2]=i; // data
spi_write_reg(TI_CCxxx0_STX,    0x0); // set in send mode 
while(1){
printk("begin \n");
spi_write_burst_reg(TI_CCxxx0_TXFIFO,txBuf,11);
spi_write_reg(TI_CCxxx0_STX,    0x0); // set in send mode 
printk("end \n");
msleep(1*1000);
spi_write_reg(TI_CCxxx0_SFTX,0);
msleep(4*1000);
}


}

static void receive_function(struct work_struct *work){


char len = spi_read_burst(TI_CCxxx0_SFTX) & 0x7F;
char buf[256];
char temp=-1;
int counter=1000;
while(gpio_get_value(BOARD_CC2500_GPO0));
while(counter > 0  ) {
if(/*len > 0 &&*/ len == temp )
break;
len = spi_read_burst(TI_CCxxx0_SFTX) & 0x7F;
temp=len;
len = spi_read_burst(TI_CCxxx0_SFTX) & 0x7F;
if(len ==0 ){
msleep(10);
len = spi_read_burst(TI_CCxxx0_SFTX) & 0x7F;
}
counter--;
}
printk("bytes in TI_CCxxx0_SFTX rxFIFO:%d \n",len);
len = spi_read_reg(TI_CCxxx0_RXFIFO);
printk("packet len in rxFIFO:%d \n",len);
if(len > 0 ) {
memset(buf,0xff,256);
buf[0]= TI_CCxxx0_RXFIFO| 0xC0;
spi_rw(cc2500->spi,buf,len+1);
int i =0;
for(i = 1; i < len;i++) {
printk("%x ",buf[i]);
if(!(i%16))
printk("\n");
}
printk("\n");
buf[0]= TI_CCxxx0_RXFIFO| 0xC0;
spi_rw(cc2500->spi,buf,3);
printk("status:%x RSSI:%x crc:%x \n",buf[0],buf[1],buf[2]);
if(!(buf[2] & 0x80)){
printk("Err: receive CRC check erro \n");
spi_write_reg(TI_CCxxx0_SFRX,0);
}
}
NO_DATA:
spi_write_reg(TI_CCxxx0_SRX,0);
enable_irq(cc2500->irq);
}