__v7_setup

.arm__HEADENTRY(stext) ARM_BE8(setendbe )@ ensure we are in BE8 mode THUMB(adrr9, BSYM(1f))@ Kernel is always entered in ARM. THUMB(bxr9)@ If this is a Thumb-2 kernel, THUMB(.thumb)@ switch to Thumb now. THUMB(1:)#ifdef CONFIG_ARM_VIRT_EXTbl__hyp_stub_install#endif@ ensure svc mode and all interrupts maskedsafe_svcmode_maskall r9mrcp15, 0, r9, c0, c0@ get processor idbl__lookup_processor_type@ r5=procinfo r9=cpuidmovsr10, r5@ invalid processor (r5=0)?，r10记录了proc_info_list结构地址 THUMB( iteq )@ force fixup-able long branch encodingbeq__error_p@ yes, error 'p'#ifdef CONFIG_ARM_LPAEmrcp15, 0, r3, c0, c1, 4@ read ID_MMFR0andr3, r3, #0xf@ extract VMSA supportcmpr3, #5@ long-descriptor translation table format? THUMB( itlo )@ force fixup-able long branch encodingblo__error_lpae@ only classic page table format#endif#ifndef CONFIG_XIP_KERNELadrr3, 2fldmiar3, {r4, r8}subr4, r3, r4@ (PHYS_OFFSET - PAGE_OFFSET)addr8, r8, r4@ PHYS_OFFSET#elseldrr8, =PLAT_PHYS_OFFSET@ always constant in this case#endif/* * r1 = machine no, r2 = atags or dtb, * r8 = phys_offset, r9 = cpuid, r10 = procinfo */bl__vet_atags#ifdef CONFIG_SMP_ON_UPbl__fixup_smp#endif#ifdef CONFIG_ARM_PATCH_PHYS_VIRTbl__fixup_pv_table#endifbl__create_page_tables/* * The following calls CPU specific code in a position independent * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of * xxx_proc_info structure selected by __lookup_processor_type * above.  On return, the CPU will be ready for the MMU to be * turned on, and r0 will hold the CPU control register value. */ldrr13, =__mmap_switched@ address to jump to after@ mmu has been enabledadrlr, BSYM(1f)@ return (PIC) addressmovr8, r4@ set TTBR1 to swapper_pg_dir ARM(addpc, r10, #PROCINFO_INITFUNC) @ __v7_setup THUMB(addr12, r10, #PROCINFO_INITFUNC) THUMB(movpc, r12)1:b__enable_mmuENDPROC(stext).ltorg

__v7_setup:adrr12, __v7_setup_stack@ the local stackstmiar12, {r0-r5, r7, r9, r11, lr}@ 寄存器入栈__v7_setup_stack是个11个word的局部栈，就在本函数后面定义，stmia表明此处用的是递增栈；bl      v7_flush_dcache_louis @ 清除数据缓存ldmiar12, {r0-r5, r7, r9, r11, lr} @ 寄存器出栈mrcp15, 0, r0, c0, c0, 0@ read main ID registerandr10, r0, #0xff000000@ ARM?teqr10, #0x41000000bne3fandr5, r0, #0x00f00000@ variantandr6, r0, #0x0000000f@ revisionorrr6, r6, r5, lsr #20-4@ combine variant and revisionubfxr0, r0, #4, #12@ primary part number@ Cortex-A7 primary part number == 0xc07/* Cortex-A8 Errata */ldrr10, =0x00000c08@ Cortex-A8 primary part numberteqr0, r10bne2f#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)teqr5, #0x00100000@ only present in r1p*mrceqp15, 0, r10, c1, c0, 1@ read aux control registerorreqr10, r10, #(1 << 6)@ set IBE to 1mcreqp15, 0, r10, c1, c0, 1@ write aux control register#endif#ifdef CONFIG_ARM_ERRATA_458693teqr6, #0x20@ only present in r2p0mrceqp15, 0, r10, c1, c0, 1@ read aux control registerorreqr10, r10, #(1 << 5)@ set L1NEON to 1orreqr10, r10, #(1 << 9)@ set PLDNOP to 1mcreqp15, 0, r10, c1, c0, 1@ write aux control register#endif#ifdef CONFIG_ARM_ERRATA_460075teqr6, #0x20@ only present in r2p0mrceqp15, 1, r10, c9, c0, 2@ read L2 cache aux ctrl registertsteqr10, #1 << 22orreqr10, r10, #(1 << 22)@ set the Write Allocate disable bitmcreqp15, 1, r10, c9, c0, 2@ write the L2 cache aux ctrl register#endifb3f/* Cortex-A9 Errata */2:ldrr10, =0x00000c09@ Cortex-A9 primary part numberteqr0, r10bne3f#ifdef CONFIG_ARM_ERRATA_742230cmpr6, #0x22@ only present up to r2p2mrclep15, 0, r10, c15, c0, 1@ read diagnostic registerorrler10, r10, #1 << 4@ set bit #4mcrlep15, 0, r10, c15, c0, 1@ write diagnostic register#endif#ifdef CONFIG_ARM_ERRATA_742231teqr6, #0x20@ present in r2p0teqner6, #0x21@ present in r2p1teqner6, #0x22@ present in r2p2mrceqp15, 0, r10, c15, c0, 1@ read diagnostic registerorreqr10, r10, #1 << 12@ set bit #12orreqr10, r10, #1 << 22@ set bit #22mcreqp15, 0, r10, c15, c0, 1@ write diagnostic register#endif#ifdef CONFIG_ARM_ERRATA_743622teqr5, #0x00200000@ only present in r2p*mrceqp15, 0, r10, c15, c0, 1@ read diagnostic registerorreqr10, r10, #1 << 6@ set bit #6mcreqp15, 0, r10, c15, c0, 1@ write diagnostic register#endif#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)ALT_SMP(cmp r6, #0x30)@ present prior to r3p0ALT_UP_B(1f)mrcltp15, 0, r10, c15, c0, 1@ read diagnostic registerorrltr10, r10, #1 << 11@ set bit #11mcrltp15, 0, r10, c15, c0, 1@ write diagnostic register1:#endif/* Cortex-A15 Errata */3:ldrr10, =0x00000c0f@ Cortex-A15 primary part numberteqr0, r10bne4f#ifdef CONFIG_ARM_ERRATA_773022cmpr6, #0x4@ only present up to r0p4mrclep15, 0, r10, c1, c0, 1@ read aux control registerorrler10, r10, #1 << 1@ disable loop buffermcrlep15, 0, r10, c1, c0, 1@ write aux control register#endif4:movr10, #0mcrp15, 0, r10, c7, c5, 0@ I+BTB cache invalidate#ifdef CONFIG_MMUmcrp15, 0, r10, c8, c7, 0@ invalidate I + D TLBs（Translation Lookaside Buffer）v7_ttb_setup r10, r4, r8, r5@ TTBCR（Translation Table Base Control Register）, TTBRx setupldrr5, =PRRR@ PRRR（Primary Region Remap Register）ldrr6, =NMRR@ NMRR（Normal Memory Remap Register,）mcrp15, 0, r5, c10, c2, 0@ write PRRRmcrp15, 0, r6, c10, c2, 1@ write NMRR#endifdsb@ Complete invalidations#ifndef CONFIG_ARM_THUMBEEmrcp15, 0, r0, c0, c1, 0@ read ID_PFR0 for ThumbEEandr0, r0, #(0xf << 12)@ ThumbEE enabled fieldteqr0, #(1 << 12)@ check if ThumbEE is presentbne1fmovr5, #0mcrp14, 6, r5, c1, c0, 0@ Initialize TEEHBR to 0mrcp14, 6, r0, c0, c0, 0@ load TEECRorrr0, r0, #1@ set the 1st bit in order tomcrp14, 6, r0, c0, c0, 0@ stop userspace TEEHBR access1:#endifadrr5, v7_crval /* AT  * TFR EV X F I D LR S  * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM  * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced  * 1 0 110 0011 1100 .111 1101 < we want  */ /* .type v7_crval, #object  v7_crval:  crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c */ldmiar5, {r5, r6} @ [r5] = clear,[r6] = mmuset ARM_BE8(orrr6, r6, #1 << 25)@ big-endian page tables#ifdef CONFIG_SWP_EMULATEorr     r5, r5, #(1 << 10)              @ set SW bit in "clear"bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"#endif   mrcp15, 0, r0, c1, c0, 0@ read control registerbicr0, r0, r5@ clear bits themorrr0, r0, r6@ set them@ r0已经使能了mmu，但是并没有写入CP15，这个操作由__enable_mmu函数来完成。 THUMB(orrr0, r0, #1 << 30)@ Thumb exceptionsmovpc, lr@ return to head.S:__retENDPROC(__v7_setup)

clear和set c1, System Control Register (SCTLR)，包括Exception Endianness bit、Interrupt Vectors Enable bit、Vectors bit.、I-cache D-cache enable、MMU enable bit等。Vectors bit决定了异常向量的入口是0x0，还是0xffff0000。

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