Xilinx FPFA中LUT4_L 元件的使用

    最近看关于FPGA的结构，发现LUT实际上是可以使用原语或者原理图中添加symbol调用。symbol information中有关于这个元件的例化原语。

----------------------------------------------------------------------------------------------------------------------

---------------VHDL Instantiation Template

Unless they already exist, copy thefollowing two statements and paste them before the entity declaration.

Library UNISIM;

use UNISIM.vcomponents.all;

 

-- LUT4_L: 4-input Look-Up Table with localoutput

 

-- Xilinx HDL Libraries Guide, version 10.1

LUT4_L_inst : LUT4_L

generic map (

INIT => X"0000")

port map (

LO => LO, -- LUT local output

I0 => I0, -- LUT input

I1 => I1, -- LUT input

I2 => I2, -- LUT input

I3 => I3 -- LUT input

);

 

-- End of LUT4_L_inst instantiation

 

----------------------------------------------------------------------------------------------------------------------

       为了验证该元件是使用方法，使用元件例化的方法调用该元件，I[3:0]相当于是LUT4的4位地址总线，为了减少综合后寄存器数量，在时钟每个上升沿使I[3:0]全部取反，代码如下：

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

---- Uncomment the following librarydeclaration if instantiating

---- any Xilinx primitives in this code.

library UNISIM;

use UNISIM.VComponents.all;

 

entity main is

 

   Port ( clk : in  STD_LOGIC;

          LO  : out STD_LOGIC

                       );

end main;

 

architecture Behavioral of main is

 

 component LUT_L is

   generic(INIT : std_logic_vector(15 downto 0));

   port ( I0,I1,I2,I3 : in std_logic;

               LO          : out std_logic);

 endcomponent ;

 

signal I0 : std_logic;

signal I1 : std_logic;

signal I2 : std_logic;

signal I3 : std_logic;

signal cnt: std_logic_vector(3 downto 0);

 

begin

 process (clk)

 begin

  ifclk 'event and clk='1' then

        cnt<= not cnt ;

                     I0<=cnt(0);

                     I1<=cnt(1);

                     I2<=cnt(2);

                     I3<=cnt(3);

       endif;

       endprocess;         

 

                     LUT4_L_inst: LUT4_L

                     genericmap (

                     INIT=> X"AAAA")

                     portmap (

                     LO=> LO, -- LUT local output

                     I0=> I0, -- LUT input

                     I1=> I1, -- LUT input

                     I2=> I2, -- LUT input

                     I3=> I3  -- LUT input

                     );

 

end Behavioral;

-------------------------------------------------Technology  Schematic----------------------------------------------------------------