Notes-20141004

The system-on-chip Design Process

Chapter 2

Design Flow

Waterfall vs Spiral

The water fall desgin flow worked well in the desings of up to 100K gates and down to 0.5 um. It has consistently produced chips that worked right the first time, although often the systems that were populated with them did not. But this flow always had problems that were populated with them did not. For large, deep sbumicron designs, this waterfall methodology simply does not work. Large systems have sufficent software content that it needs the hardware and software must be developed concurrently to ensure correct system functionality.

Top-down vs. Bottom-up

real world trams usually use a mixture of top-down and bottom-up methodologies.

Top-down: a recursive routine, from the specification and decomposition to integration and verification. (Problems, block could not be realized)

Botton-up: Libraries of reusable hard and soft macros.(Verified blocks.)

Construct by Correction

Opposited with the correction of construction where the intent is to get the design completely right during the first pass, this emphasized  to make the first pass through the design cycle from the architecture to the layout as soon as possible, allowing for multiple iterations through the entire process.

Going back to the specification after the initial layout of a chip is expensive; we want to do it as few times as possible, and as early in the design cycle as possible. The inevitability of iteration shoulbe never be used as an excuse to short-change the specification process. Spending time in carefully specifying a design is the best way to minimize the number of interative loops and to minimize the mount of time spent in each loop.

The rapid development of clear, complete, and consistent specifications is a difficult probem.

The Specification Problems

Specification Requirements:

Hardware:

Functionality, External interfaces to other hardware(pins, buses, and how to use them), Interface to SW(Register definitions), Timing, Performance, Physical design issues such as area and power

Software:

Functionality, Timing, Performance, Interface to HW, SW structure, Kernel.

Including: Formal Specification and executable specification.