关于NIOS中Avalon总线的问题分析

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关于nios中的Avalon总线，首先明确一点就是其是八位寻址的，这个很重要。

曾经对ssram操作过，这里不讨论读写时序的问题，只是关注avalon对其的地址分配，对于verilog编写的ip核，只给出部分参数。

ssram的芯片接口为：

inout[15:0]      mem_data;output[20:0]mem_addr;

地址21bit，数据16bit。和avalon（8bit寻址）连接。如下为连接avalon总线：

input[20:0] avs_addr;input[15:0]avs_write_data;output[15:0]avs_read_data;

我们再来看看实际nios为此付出的寻址空间：（下面一条红线标识）

实际分配了0x400000的大小空间，再分析此空间在nios中需要22bit才能寻址到，这下可以明白了，

所以这个问题可以理解了。

对于自己写的IP在c语言操作时，要注意偏移地址问题。

如下有个项目实例：

/*usage:dsp emif interface.address allocation: 0x0000~0x1fff: dual port ram for writing 0x0000~0x3fff: dual port ram for reading 0x4000:write and read ce_ccd_nios_n 0x4004:write and read dsp_gp5_pre*/module dsp_emif_ip(//avalon slave                  input clk,input [31:0]wdata,output [31:0]rdata,input [12:0]addr,input wren,input rden,input chipselect,//portinput img_wr_en,input [23:0] img_data,input [11:0] img_addr,input img_wr_clk,input img_wr_ok,output dsp_gp5,inout [31:0] dsp_data,input [11:0] dsp_addr,input dsp_oe_n,input dsp_we_n,input dsp_ce4_n,input dsp_emif_clk               );wire dsp_rden;wire dsp_wren;wire [31:0] dsp_wdata;wire [31:0] dsp_rdata;assign dsp_rden=(!dsp_oe_n)&(!dsp_ce4_n);assign dsp_wren=(!dsp_we_n)&(!dsp_ce4_n);//ce_ccd_nios_n=0->boot;ce_ccd_nios_n=1->image transportreg ce_ccd_nios_n;reg dsp_gp5_pre;initial begince_ccd_nios_n = 0;endalways @(posedge clk )beginif (chipselect && wren)begincase ({addr[12:0], 2'b0})15'h4000:ce_ccd_nios_n <= wdata[0];15'h4004:dsp_gp5_pre <= wdata[0];endcaseendendwire boot_ram_wren;assign boot_ram_wren = (!ce_ccd_nios_n && addr[12] == 1'b0) ? wren : 0;assign dsp_gp5 = ce_ccd_nios_n ? img_wr_ok : dsp_gp5_pre;wire [31:0] read_data_1;assign rdata = ({addr[12:0], 2'b0} == 15'h4000) ? {31'd0, ce_ccd_nios_n} : ({addr[12:0], 2'b0} == 15'h4004) ? {31'b0, dsp_gp5_pre} :(addr[12] == 1'b0) ? read_data_1 : 32'b0;wire [31:0] dsp_rdata_boot;wire [31:0] dsp_rdata_image;//nios write, dsp readdp_ram_32bitdsp_boot_inst (.data ( wdata ),.rdaddress ( dsp_addr[10:0] ),.rdclock ( dsp_emif_clk ),.rden (dsp_rden ),.wraddress (addr[10:0]),.wrclock ( clk),.wren (boot_ram_wren),.q ( dsp_rdata_boot ));//external signal write(CCD), dsp readram_win_originrgbccd_to_dsp_inst (.data ( img_data ),.rdaddress ( dsp_addr ),.rdclock ( dsp_emif_clk ),.rden ( dsp_rden ),.wraddress ( img_addr ),.wrclock ( img_wr_clk ),.wren ( img_wr_en ),.q ( dsp_rdata_image[23:0] ));//dsp write, nios readram_win_originrgbdsp_to_nios_inst (.data (dsp_wdata[23:0]),.rdaddress (addr[11:0]),.rdclock (clk),.rden (addr[12] == 0 ? rden : 1'b0),.wraddress (dsp_addr[11:0]),.wrclock (dsp_emif_clk ),.wren (dsp_wren),.q (read_data_1[23:0 ]));assign dsp_rdata = ce_ccd_nios_n ? dsp_rdata_image : dsp_rdata_boot;assign dsp_wdata = !dsp_rden ? dsp_data : 32'bz;assign dsp_data = dsp_rden ? dsp_rdata : 32'bz;endmodule

上面是一个为dsp的emif接口写的一个IP，对于DSP的EMIF这里不做过多讨论。

由上面说明：与nios的address的连接为[14:2] <==> addr[12:0]

address allocation:nios address [14:0]
0x0000~0x1fff: dual port ram for writing
0x0000~0x3fff: dual port ram for reading
0x4000:write and read ce_ccd_nios_n
0x4004:write and read dsp_gp5_pre

这是地址分配。通过addr[12]完成不同地址的读写。

然后再看看在nios编程是如何，完成软件编写的。下面为两个寄存器的偏移地址

#define CE_CCD_NIOS_N_OFF 0x4000
#define DSP_GP5_PRE_OFF 0x4004

系统给出的IP核的定义为

#define ALT_MODULE_CLASS_dsp_emif dsp_emif_ip
#define DSP_EMIF_BASE 0x60000 <====为基地址
#define DSP_EMIF_IRQ -1
#define DSP_EMIF_IRQ_INTERRUPT_CONTROLLER_ID -1
#define DSP_EMIF_NAME "/dev/dsp_emif"
#define DSP_EMIF_SPAN 32768
#define DSP_EMIF_TYPE "dsp_emif_ip"

所以这样基本清楚了

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有时所写的offset也有所区别，这主要是Native bus和Dynamic bus的区别。及IOWR和IORD_32DIRECT的区别。

为了深入理解，直接给出函数定义，在io.h中

#ifndef __IO_H__#define __IO_H__/*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             ** Altera does not recommend, suggest or require that this reference design    ** file be used in conjunction or combination with any other product.          *******************************************************************************//* IO Header file for Nios II Toolchain */#include "alt_types.h"#ifdef __cplusplusextern "C"{#endif /* __cplusplus */#ifndef SYSTEM_BUS_WIDTH#error SYSTEM_BUS_WIDTH undefined#endif<span style="color:#ff0000;">/* Dynamic bus access functions */</span><span style="color:#ff0000;">#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \  ((void *)(((alt_u8*)BASE) + (OFFSET)))</span>#define IORD_32DIRECT(BASE, OFFSET) \  __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)))#define IORD_16DIRECT(BASE, OFFSET) \  __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)))#define IORD_8DIRECT(BASE, OFFSET) \  __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)))#define IOWR_32DIRECT(BASE, OFFSET, DATA) \  __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA))#define IOWR_16DIRECT(BASE, OFFSET, DATA) \  __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA))#define IOWR_8DIRECT(BASE, OFFSET, DATA) \  __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA))<span style="color:#ff0000;">/* Native bus access functions */</span><span style="color:#ff0000;">#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \  ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8))))</span>#define IORD(BASE, REGNUM) \  __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)))#define IOWR(BASE, REGNUM, DATA) \  __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA))#ifdef __cplusplus}#endif#endif /* __IO_H__ */

这样就明白了

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