Kinetis SRAM
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All Kinetis K-series devices include two blocks of on-chip SRAM. The first block (SRAM_L) is mapped to the CODE bus,
and the second block (SRAM_U) is mapped to the system bus. The memory itself can be accessed in a single cycle, but
because instruction accesses to the system bus incurs a one clock delay at the core, SRAM_U instruction accesses take at
least two clocks.
SRAM_L is the only memory where code or data can be stored and the core is almost always guaranteed a single cycle
access. For this reason, it makes sense to use the SRAM_L block as much as possible. This is a good area for storing critical
code.
and the second block (SRAM_U) is mapped to the system bus. The memory itself can be accessed in a single cycle, but
because instruction accesses to the system bus incurs a one clock delay at the core, SRAM_U instruction accesses take at
least two clocks.
SRAM_L is the only memory where code or data can be stored and the core is almost always guaranteed a single cycle
access. For this reason, it makes sense to use the SRAM_L block as much as possible. This is a good area for storing critical
code.
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