uboot中 Tiny 4412和smdk 4212的一些不同

Tiny4412.cint board_init(void)#ifdef CONFIG_HAS_PMIC 注释掉了和i2c的读写部分............#else/* fixed voltage */写死电压值#define VDDM_F(vm)(#vm)#define SHOW_FIXED_VDD(lab, a)printf("%s: %s\n", lab, VDDM_F(a))printf("\n");SHOW_FIXED_VDD("vdd_arm", CONFIG_PM_VDD_ARM);SHOW_FIXED_VDD("vdd_int", CONFIG_PM_VDD_INT);SHOW_FIXED_VDD("vdd_mif", CONFIG_PM_VDD_MIF);       #endif        //设置 Tiny4412 machine ID 4608 */        #ifdef CONFIG_TINY4412Agd->bd->bi_arch_number = MACH_TYPE_TINY4412;#elseif (((PRO_ID & 0x300) >> 8) == 2)gd->bd->bi_arch_number = MACH_TYPE_C210;elsegd->bd->bi_arch_number = MACH_TYPE_V310;#endifTiny4412.h  #define CONFIG_PM#define CONFIG_PM_VDD_ARM1.2#define CONFIG_PM_VDD_INT1.0#define CONFIG_PM_VDD_G3D1.1#define CONFIG_PM_VDD_MIF1.1#define CONFIG_PM_VDD_LDO141.8clock_init_tiny4412.S#include "tiny4212_val.h"//注释掉了C2C部分和DMC部分（power modes change when you enable c2c；DMC block can be automatically in retention state according to C2C state when ENABLE_C2C field of C2C_CTRL register is set to "1".）#ifdef CONFIG_C2C/* TODO: update it *//* check C2C_CTRL enable bit */ldr r3, =S5PV310_POWER_BASEldr r1, [r3, #C2C_CTRL_OFFSET]and r1, r1, #1cmp r1, #0bne v310_2@ ConControl#ifdef MEM_DLLl_ONldrr0, =APB_DMC_0_BASEldrr1, =0x7F10100Aldrr2, =DMC_PHYCONTROL0strr1, [r0, r2]ldrr1, =0xE0000084ldrr2, =DMC_PHYCONTROL1strr1, [r0, r2]ldrr1, =0x7F10100Bldrr2, =DMC_PHYCONTROL0strr1, [r0, r2]/* wait ?us */movr1, #0x200008:subsr1, r1, #1bne8bldrr1, =0x0000008Cldrr2, =DMC_PHYCONTROL1strr1, [r0, r2]ldrr1, =0x00000084ldrr2, =DMC_PHYCONTROL1strr1, [r0, r2]/* wait ?us */movr1, #0x200009:subsr1, r1, #1bne9bldrr0, =APB_DMC_1_BASEldrr1, =0x7F10100Aldrr2, =DMC_PHYCONTROL0strr1, [r0, r2]ldrr1, =0xE0000084ldrr2, =DMC_PHYCONTROL1strr1, [r0, r2]ldrr1, =0x7F10100Bldrr2, =DMC_PHYCONTROL0strr1, [r0, r2]/* wait ?us */movr1, #0x2000010:subsr1, r1, #1bne10bldrr1, =0x0000008Cldrr2, =DMC_PHYCONTROL1strr1, [r0, r2]ldrr1, =0x00000084ldrr2, =DMC_PHYCONTROL1strr1, [r0, r2]/* wait ?us */movr1, #0x2000011:subsr1, r1, #1bne11b#endifldrr0, =APB_DMC_0_BASEldrr1, =0x0FFF30FAldrr2, =DMC_CONCONTROLstrr1, [r0, r2]ldrr0, =APB_DMC_1_BASEldrr1, =0x0FFF30FAldrr2, =DMC_CONCONTROLstrr1, [r0, r2]ldrr0, =APB_DMC_0_BASEldrr1, =0x00202533ldrr2, =DMC_MEMCONTROLstrr1, [r0, r2]ldrr0, =APB_DMC_1_BASEldrr1, =0x00202533ldrr2, =DMC_MEMCONTROLstrr1, [r0, r2]v310_2:#endif /* CONFIG_C2C */lowlevel_init.S: //关pmic，设置mmu，增加调试打印和点灯程序。/* led (GPM4_0~3) on */ldrr0, =0x110002E0ldrr1, =0x00001111strr1, [r0]ldrr1, =0x0estrr1, [r0, #0x04] */#if defined(CONFIG_HAS_PMIC)blpmic_init#endif#if CONFIG_LL_DEBUGmovr4, #0x4000.L0:subr4, r4, #1cmpr4, #0bne.L0movr0, #'\r'bluart_asm_putcmovr0, #'\n'bluart_asm_putcldrr1, =0x40000000ldrr2, =0x87654321strr2, [r1]strr2, [r1, #0x04]strr2, [r1, #0x08]ldrr2, =0x55aaaa55strr2, [r1, #0x10]nopmovr4, #0xC0000.L1:subsr4, r4, #1bne.L1ldrr0, [r1]bluart_asm_putxmovr0, #'.'bluart_asm_putcldrr0, [r1, #0x04]bluart_asm_putxmovr0, #'.'bluart_asm_putcldrr0, [r1, #0x08]bluart_asm_putxmovr0, #'.'bluart_asm_putcldrr0, [r1, #0x10]bluart_asm_putxmovr0, #'>'bluart_asm_putc#endif /* CONFIG_LL_DEBUG */#if CONFIG_LL_DEBUG.globl uart_asm_putcuart_asm_putc:push{r9}ldrr9, =S5PV310_UART_CONSOLE_BASEstrr0, [r9, #UTXH_OFFSET]ldrr9, =[e-mail]:subr9, r9, #1cmpr9, #0bne.Luartputcpop{r9}movpc, lr.globl uart_asm_putxuart_asm_putx:stmfd sp!, {r3, r4, r5, lr}movr5, r0movr4, #28.Luartputx:movr0, r5, asr r4andr0, r0, #15cmpr0, #9addler0, r0, #48addgtr0, r0, #55bluart_asm_putcsubr4, r4, #4cmnr4, #4bne.Luartputxldmfd sp!, {r3, r4, r5, pc}#endif /* CONFIG_LL_DEBUG */mmu_table:.set __base,0// Access for iRAM.rept 0x200FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr// Not Allowed.rept 0x400 - 0x200.word 0x00000000.endr.set __base,0x400// 1024MB for SDRAM with cacheable.rept 0x800 - 0x400FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr// access is not allowed..rept 0xc00 - 0x800.word 0x00000000.endrMakefile：COBJS-y:= tiny4412.oCOBJS-y+= pmic.oSOBJS:= lowlevel_init.oSOBJS+= mem_init_tiny4412.oSOBJS+= clock_init_tiny4412.otiny4412_val.h：/* ARM_CLOCK_1Ghz */#elif defined(CONFIG_CLK_ARM_1000_APLL_1000)#define APLL_MDIV0x7D#define APLL_PDIV0x3#define APLL_SDIV0x0/* CLK_DIV_CPU0*/#define APLL_RATIO0x1#define CORE_RATIO0x0#define CORE2_RATIO0x0#define COREM0_RATIO0x2#define COREM1_RATIO0x5#define PERIPH_RATIO0x7#define ATB_RATIO0x4#define PCLK_DBG_RATIO0x1#define CLK_DIV_CPU0_VAL        ((CORE2_RATIO << 28)    \                                | (APLL_RATIO << 24)    \                                | (PCLK_DBG_RATIO << 20)\                                | (ATB_RATIO << 16)     \                                | (PERIPH_RATIO <<12)   \| (COREM1_RATIO << 8)   \                                | (COREM0_RATIO << 4)   \                                | (CORE_RATIO))#define CLK_DIV_CPU1_VAL((CORES_RATIO << 8) \                                |  (HPM_RATIO << 4) \                                | (COPY_RATIO))#elif defined(CONFIG_CLK_BUS_DMC_200_400)#define MPLL_MDIV0x64#define MPLL_PDIV0x3#define MPLL_SDIV0x0/* APLL_CON1*/#define APLL_CON1_VAL(0x00803800)/* MPLL_CON1*/#define MPLL_CON1_VAL (0x00803800)#define EPLL_MDIV0x40#define EPLL_PDIV0x2#define EPLL_SDIV0x3#define EPLL_CON1_VAL0x66010000#define EPLL_CON2_VAL0x00000080#define VPLL_MDIV0x48#define VPLL_PDIV0x2#define VPLL_SDIV0x3#define VPLL_CON1_VAL0x66010000#define VPLL_CON2_VAL0x00000080/* Set PLL */#define set_pll(mdiv, pdiv, sdiv)(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)#define APLL_CON0_VALset_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV)#define MPLL_CON0_VALset_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV)#define EPLL_CON0_VALset_pll(EPLL_MDIV,EPLL_PDIV,EPLL_SDIV)#define VPLL_CON0_VALset_pll(VPLL_MDIV,VPLL_PDIV,VPLL_SDIV)/* CLK_SRC_CPU*//* 0 = MOUTAPLL,  1 = SCLKMPLL*/#define MUX_HPM_SEL_MOUTAPLL0#define MUX_HPM_SEL_SCLKMPLL1#define MUX_CORE_SEL_MOUTAPLL0#define MUX_CORE_SEL_SCLKMPLL1/* 0 = FILPLL, 1 = MOUT */#define MUX_MPLL_SEL_FILPLL0#define MUX_MPLL_SEL_MOUTMPLLFOUT1#define MUX_APLL_SEL_FILPLL0#define MUX_APLL_SEL_MOUTMPLLFOUT1#define CLK_SRC_CPU_VAL_FINPLL        ((MUX_HPM_SEL_MOUTAPLL << 20)    \                                | (MUX_CORE_SEL_MOUTAPLL <<16)   \                                | (MUX_MPLL_SEL_FILPLL << 8)   \                                | (MUX_APLL_SEL_FILPLL <<0))#define CLK_SRC_CPU_VAL_MOUTMPLLFOUT((MUX_HPM_SEL_MOUTAPLL << 20)    \                                | (MUX_CORE_SEL_MOUTAPLL <<16)   \                                | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)   \                                | (MUX_APLL_SEL_MOUTMPLLFOUT <<0))/* CLK_SRC_DMC*/#define MUX_PWI_SEL        0x0#define MUX_CORE_TIMERS_SEL0x0#define MUX_DPHY_SEL0x0#define MUX_DMC_BUS_SEL0x0#define CLK_SRC_DMC_VAL         ((MUX_PWI_SEL << 16)            \                                | (MUX_CORE_TIMERS_SEL << 12)   \                                | (MUX_DPHY_SEL << 8)           \                                | (MUX_DMC_BUS_SEL << 4))/* CLK_DIV_DMC0*/#define CORE_TIMERS_RATIO0x0#define COPY2_RATIO0x0#define DMCP_RATIO0x1#define DMCD_RATIO0x1#define DMC_RATIO0x1#define DPHY_RATIO0x1#define ACP_PCLK_RATIO0x1#define ACP_RATIO0x3#define CLK_DIV_DMC0_VAL((CORE_TIMERS_RATIO << 28) \| (COPY2_RATIO << 24) \| (DMCP_RATIO << 20)\| (DMCD_RATIO << 16)\| (DMC_RATIO << 12)\| (DPHY_RATIO << 8)\| (ACP_PCLK_RATIO << 4)\| (ACP_RATIO))#define CLK_DIV_DMC1_VAL0x07071713/* CLK_SRC_TOP0*/#define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166*/#define MUX_ACLK_133_SEL0x0/* 0 = SCLKMPLL, 1 = SCLKAPLL*/#define MUX_ACLK_160_SEL0x0#define MUX_ACLK_100_SEL0x0#define MUX_ACLK_200_SEL0x0#define MUX_VPLL_SEL0x1#define MUX_EPLL_SEL0x1#define CLK_SRC_TOP0_VAL((MUX_ONENAND_SEL << 28)\| (MUX_ACLK_133_SEL << 24)\| (MUX_ACLK_160_SEL << 20)\| (MUX_ACLK_100_SEL << 16)\| (MUX_ACLK_200_SEL << 12)\| (MUX_VPLL_SEL << 8)\| (MUX_EPLL_SEL << 4))/* CLK_SRC_TOP1*/#define VPLLSRC_SEL0x0/* 0 = FINPLL, 1 = SCLKHDMI27M*/#define CLK_SRC_TOP1_VAL(0x01111000)//#define CLK_SRC_TOP1_VAL(VPLLSRC_SEL)/* CLK_DIV_TOP*/#define ACLK_400_MCUISP_RATIO0x1#define ACLK_266_GPS_RATIO0x2#define ONENAND_RATIO0x1#define ACLK_133_RATIO0x5#define ACLK_160_RATIO0x4#define ACLK_100_RATIO0x7#define ACLK_200_RATIO0x4#define CLK_DIV_TOP_VAL((ACLK_400_MCUISP_RATIO << 24) \| (ACLK_266_GPS_RATIO << 20) \| (ONENAND_RATIO << 16) \| (ACLK_133_RATIO << 12) \| (ACLK_160_RATIO << 8)\| (ACLK_100_RATIO << 4)\| (ACLK_200_RATIO))/* CLK_SRC_LEFTBUS*/#define CLK_SRC_LEFTBUS_VAL(0x10)/* CLK_DIV_LEFRBUS*/#define GPL_RATIO0x1#define GDL_RATIO0x3#define CLK_DIV_LEFRBUS_VAL((GPL_RATIO << 4) \| (GDL_RATIO))/* CLK_SRC_RIGHTBUS*/#define CLK_SRC_RIGHTBUS_VAL(0x10)/* CLK_DIV_RIGHTBUS*/#define GPR_RATIO0x1#define GDR_RATIO0x3#define CLK_DIV_RIGHTBUS_VAL((GPR_RATIO << 4) \| (GDR_RATIO))/* APLL_LOCK*/#define APLL_LOCK_VAL(APLL_PDIV * 270)/* MPLL_LOCK*/#define MPLL_LOCK_VAL(MPLL_PDIV * 270)/* EPLL_LOCK*/#define EPLL_LOCK_VAL(EPLL_PDIV * 3000)/* VPLL_LOCK*/#define VPLL_LOCK_VAL(VPLL_PDIV * 3000)/* CLK_SRC_PERIL0*/#define PWM_SEL0#define UART5_SEL6#define UART4_SEL6#define UART3_SEL6#define UART2_SEL6#define UART1_SEL6#define UART0_SEL6#define CLK_SRC_PERIL0_VAL((PWM_SEL << 24)\| (UART5_SEL << 20)  \| (UART4_SEL << 16) \| (UART3_SEL << 12) \| (UART2_SEL<< 8)\| (UART1_SEL << 4)\| (UART0_SEL))/* CLK_DIV_PERIL0*/#if defined(CONFIG_CLK_BUS_DMC_165_330)#define UART5_RATIO7#define UART4_RATIO7#define UART3_RATIO7#define UART2_RATIO7#define UART1_RATIO7#define UART0_RATIO7#define CLK_DIV_PERIL0_VAL((UART5_RATIO << 20) \| (UART4_RATIO << 16) \| (UART3_RATIO << 12)\| (UART2_RATIO << 8)\| (UART1_RATIO << 4)\| (UART0_RATIO))#define MPLL_DEC(MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))#define SCLK_UARTMPLL_DEC / (UART1_RATIO+1)#define UART_UBRDIV_VAL0x35    /* (SCLK_UART/(115200*16) -1) */#define UART_UDIVSLOT_VAL0x4/*((((SCLK_UART*10/(115200*16) -10))%10)*16/10)*/比较tiny4412_val.h和smdk4212_val.h不同的地方主要是：设置CONFIG_CLK_ARM_1200_APLL_1400即是主频为1.4G。DMC1的设置UART*_RATIO设置