Verilog中Task语句可综合设计实例

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此程序在Xilinx ISE综合工具中实现了综合和布局布线后仿真，功能正确。感兴趣的可以一起讨论研究。

`timescale 1ns / 1ps

module TaskLearn(clk , reset , signal);

input clk , reset;
output reg signal;
reg [3:0]counter;

reg [3:0]state;
parameter idle   = 4'b0000;
parameter state1 = 4'b0001;
parameter state2 = 4'b0010;
parameter state3 = 4'b0100;
parameter state4 = 4'b1000;

always@(posedge clk)
begin
if(reset)
    begin
    state <= idle;
    signal <= 1'bZ;
    end
else
    case(state)
        idle:
            begin
            state <= state1;
            signal <= 1;
            end
        state1:
            begin
            signal <= 0;
            hold_10_clk(state2);
            end
        state2:
            begin
            signal <= 1;
            state <= state3;
            end
        state3:
            begin
            hold_10_clk(state4);
            //state <= state4;综合报告中采用两种方法资源使用几乎一样
            signal <= 0;
            end
        state4:
            begin
            state <= state1;
            signal <= 1;
            end
        default:
        state <= idle;
    endcase
end
//-----------------------------------------------------------------------------
//延时10个周期控制
task hold_10_clk;
    input [3:0]s;
    if(counter < 10)
        counter <= counter + 1;
    else
    begin
        counter <= 0;
        state <= s;
    end
endtask
//-----------------------------------------------------------------------------
endmodule

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