cpu变频原理调用clk_prepare_enable异常调试纪实

On spreadtrum platform, we use dvfs to adjust the cpu's frequency and voltage. Instead of calling the standard clock api, the dvfs owner operates the register directly to adjust the cpu's clock. It has been proved when somebody else new take charge of maintain the code or a new chip need use this strategy, it will occurs various unexpected problems. To avoid of this, the dvfs owner start to modify the code.

But after changing to standard clock api, we found that the the smartphone holds or panicat high probability.  Depend on our

analysis, we found that after calling clk_prepare_enable() instead of operate the mpll ref select register, it will occurs this issue and the scene is different every time. We don't kown why. But we suspect the vddarm core maybe lower than expected

 From the following test, we found the root cause finally

1 improve vddarm voltage, close mpll,  X

2 don't close mpll, Y

 Then we the check the different logic between clk_prepare_enable() and set mpll refer register. Set mpll refer register will delay 500us, but clk_prepare_enable() have no delay. So the root case is after enable mpll, it should be wait a moment to assure mpll stable. Or else the mpll will not lock the corrent value.