s5pv210的时钟系统和时钟的编程方式

来源：互联网发布：数据机房建设方案编辑：程序博客网时间：2024/04/30 09:37

编程的基本的过程：
  1，使能PLL配置寄存器[31]=1,设置PMS
  2，设置locktime
  3，设置分频寄存器CLK_DIV
  4, 设置时钟源 CLK_SRC

P M S
APLL PMS Value: 3 125 1 (1000M)
MPLL PMS Value: 12 667 1 (667M)
EPLL PMS Value: 3 48 2 (96M)
VPLL PMS Value: 6 108 3 (54M)

Turn on a PLL
(A,M,E,V)PLL_CON[31] = 1; // Power on a PLL (Refer to (A, M, E, V) PLL_CON SFR)
PLL_CON[31] = 1;

1.寄存器：
3.7.2 PLL CONTROL REGISTERS
3.7.2.1 PLL Control Registers (APLL_LOCK / MPLL_LOCK / EPLL_LOCK / VPLL_LOCK)
• (APLL_LOCK, R/W, Address = 0xE010_0000)
• (MPLL_LOCK, R/W, Address = 0xE010_0008)
• (EPLL_LOCK, R/W, Address = 0xE010_0010)
• (VPLL_LOCK, R/W, Address = 0xE010_0020)

APLL_LOCK : 30us
1/24 * 10 ^6 * n = 30 * 10^-6
  n = 30 * 24;
MPLL_LOCK : 200us
  n = 200 * 24
EPLL_LOCK : 375us
  n = 375 * 24

VPLL_LOCK : 100us
  n = 100 * 24

APLL_LOCK = 0x2d0
MPLL_LOCK = 0x12c0
EPLL_LOCK = 0x2328
VPLL_LOCK = 0x960

2.倍频：
对于APLL：
(1<<31)|(125<<16)|(3<<8)|(1<<0)
对于MPLL：
(1<<31)|(667<<16)|(12<<8)|(1<<0)
对于EPLL：
(1<<31)|(48<<16)|(3<<8)|(2<<0)
对于VPLL：
(1<<31)|(108<<16)|(6<<8)|(3<<0)

3.分频：
Clock Divider Control Register (CLK_DIV0, R/W, Address = 0xE010_0300)

APLL_RATIO [2:0]
ARMCLK = MOUT_MSYS / (APLL_RATIO + 1)

A2M_RATIO [6:4]
SCLKA2M = SCLKAPLL / (A2M_RATIO + 1)

HCLK_MSYS_RATIO [10:8]
HCLK_MSYS = ARMCLK / (HCLK_MSYS_RATIO + 1)

PCLK_MSYS_RATIO [14:12]
PCLK_MSYS = HCLK_MSYS / (PCLK_MSYS_RATIO + 1)

HCLK_DSYS_RATIO [19:16]
HCLK_DSYS = MOUT_DSYS / (HCLK_DSYS_RATIO + 1)

PCLK_DSYS_RATIO [22:20]
PCLK_DSYS = HCLK_DSYS / (PCLK_DSYS_RATIO + 1)

HCLK_PSYS_RATIO [27:24]
HCLK_PSYS = MOUT_PSYS / (HCLK_PSYS_RATIO + 1)

PCLK_PSYS_RATIO [30:28]
PCLK_PSYS = HCLK_PSYS / (PCLK_PSYS_RATIO + 1)

ARMCLK（1000） = MOUT_MSYS(1000) / (APLL_RATIO + 1) // 1/1   APLL_RATIO=0
SCLKA2M（1000） = SCLKAPLL （1000）/ (A2M_RATIO + 1) // 1/1      A2M_RATIO = 0
HCLK_MSYS(200) = ARMCLK(1000) / (HCLK_MSYS_RATIO + 1) // 1/5   HCLK_MSYS_RATIO =4
PCLK_MSYS(100) = HCLK_MSYS(200) / (PCLK_MSYS_RATIO + 1) //1/2   PCLK_MSYS_RATIO = 1
HCLK_DSYS(166) = MOUT_DSYS (667)/ (HCLK_DSYS_RATIO + 1) // 1/4   HCLK_DSYS_RATIO = 3

PCLK_DSYS(83) = HCLK_DSYS (166)/ (PCLK_DSYS_RATIO + 1) //1/2 PCLK_DSYS_RATIO=1
HCLK_PSYS(133) = MOUT_PSYS(667) / (HCLK_PSYS_RATIO + 1) // 1/5 HCLK_PSYS_RATIO = 4
PCLK_PSYS(66) = HCLK_PSYS(133) / (PCLK_PSYS_RATIO + 1) //(1/2) PCLK_PSYS_RATIO = 1

//CLK_DIV0 = (0<<0) | (0<<4)|(4<<8) | (1<<12)|(3<<16)|(4<<20)|(1<<24)--之前出错的地方
CLK_DIV0 = (0<<0)| (0<<4)|(4<<8) | (1<<12)|(3<<16)|(1<<20)|(4<<24)|(1<<28)

CLK_DIV6, R/W, Address = 0xE010_0318
CLK_DIV6 |= (4<<28)

4.时钟源：
3.7.3.1 Clock Source Control Registers (CLK_SRC0, R/W, Address = 0xE010_0200)
CLK_SRC0 = 0x1111;

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