stm32F051 HSI 时钟作为主时钟

最近要用 stm32F051， 因为板子比较小，故就没有外部晶体，想用内部8M RC为作48M系统时钟的来源。但是一下子，没弄出来，上网找了找，其实想快弄出来。结果还是看了一下代码，和手册，既然花了时间，就分享给大家吧，免得再耽误时间了。

两种方法：

1. 在系统启动时自动检测，没有外部晶体，就用内部HSI作为时钟源，代码如下：

/**  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash  *         settings.  * @note   This function should be called only once the RCC clock configuration  *         is reset to the default reset state (done in SystemInit() function).  * @param  None  * @retval None  */static void SetSysClock(void){  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;/******************************************************************************//*            PLL (clocked by HSE) used as System clock source                *//******************************************************************************/    /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/  /* Enable HSE */      RCC->CR |= ((uint32_t)RCC_CR_HSEON);   /* Wait till HSE is ready and if Time out is reached exit */  do  {    HSEStatus = RCC->CR & RCC_CR_HSERDY;    StartUpCounter++;    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));  if ((RCC->CR & RCC_CR_HSERDY) != RESET)  {    HSEStatus = (uint32_t)0x01;  }  else  {    HSEStatus = (uint32_t)0x00;  }    if (HSEStatus == (uint32_t)0x01)  {    /* Enable Prefetch Buffer and set Flash Latency */    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;     /* HCLK = SYSCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;          /* PCLK = HCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;    /* PLL configuration */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);                /* Enable PLL */    RCC->CR |= RCC_CR_PLLON;    /* Wait till PLL is ready */    while((RCC->CR & RCC_CR_PLLRDY) == 0)    {    }    /* Select PLL as system clock source */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;        /* Wait till PLL is used as system clock source */    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)    {    }  }  else  { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */ /* enable HSI */RCC->CR &= ~RCC_CR_HSION;while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET){}    /* Enable Prefetch Buffer and set Flash Latency */    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;    /* HCLK = SYSCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;          /* PCLK = HCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;    /* PLL configuration */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLMULL12);    /* Enable PLL */    RCC->CR |= RCC_CR_PLLON;    /* Wait till PLL is ready */    while((RCC->CR & RCC_CR_PLLRDY) == 0)    {}    /* Select PLL as system clock source */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;        /* Wait till PLL is used as system clock source */    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)    {}  }  }

将system_stm32f0xx.c  中的 SetSysClock() 函数的 else 填充加粗部分代码，这样，HSE启动不了的时候，自动转HSI

2. 自己写函数，可以通过这个函数，在有外部晶体的时候主动切换到HSI，代码如下：

/******************************************************************************* * Function Name: system_clk_config* Description:** Input Params:** Return:********************************************************************************/void system_clk_config_HSI(void){<span style="white-space:pre"></span>RCC_DeInit();/* enable HSI */RCC_HSICmd(ENABLE);while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET){}/* Enable Prefetch Buffer */FLASH_PrefetchBufferCmd(ENABLE);/* set Flash Latency, 0-24M: FLASH_Latency_0, 24M < sysclk <48M: FLASH_Latency_1*/FLASH_SetLatency(FLASH_Latency_1);/* Configures the AHB clock (HCLK)  */RCC_HCLKConfig(RCC_CFGR_HPRE_DIV1);/* Configures the APB clock (PCLK) */RCC_PCLKConfig(RCC_CFGR_PPRE_DIV1);/* Configures PLL source, (8M/2) * 12 = 48M */RCC_PLLConfig(RCC_CFGR_PLLSRC_HSI_DIV2, RCC_CFGR_PLLMULL12); RCC_PLLCmd(ENABLE);while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){}/* Configures system clock source */RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);    /* Wait till PLL is used as system clock source */    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)    {}}

注：下面要以看到STM32F051的时钟树，HSI供给PLL的时候是强制 2分频的，所以到PLL就只有 4M了，