Xilinx 双口RAM Ipcore Teset(VHDL)
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Xilinx 双口RAMIpcore Teset(VHDL)
CPLD/FPGA2010-03-19 11:39:14 阅读77 评论0 字号:大中小
这几天能Xilinx的双口RAM CORE,终于能好了。现将代码和时序贴出来。
代码:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY DoubleRamTest IS
END DoubleRamTest;
ARCHITECTURE behavior OF DoubleRamTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPTest
PORT(
clka : IN std_logic;
ena : IN std_logic;
wea : IN std_logic_vector(0 downto 0);
addra : IN std_logic_vector(9 downto 0);
dina : IN std_logic_vector(15 downto 0);
douta : OUT std_logic_vector(15 downto 0);
clkb : IN std_logic;
enb : IN std_logic;
web : IN std_logic_vector(0 downto 0);
addrb : IN std_logic_vector(9 downto 0);
dinb : IN std_logic_vector(15 downto 0);
doutb : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clka : std_logic := '0';
signal ena : std_logic := '0';
signal wea : std_logic_vector(0 downto 0) := (others => '0');
signal addra : std_logic_vector(9 downto 0) := (others => '0');
signal dina : std_logic_vector(15 downto 0) := (others => '0');
signal clkb : std_logic := '0';
signal enb : std_logic := '0';
signal web : std_logic_vector(0 downto 0) := (others => '0');
signal addrb : std_logic_vector(9 downto 0) := (others => '0');
signal dinb : std_logic_vector(15 downto 0) := (others => '0');
signal count:std_logic_vector(15 downto 0) := (others =>'0');
--Outputs
signal douta : std_logic_vector(15 downto 0);
signal doutb : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clka_period : time := 1us;
constant clkb_period : time := 1us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IPTest PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
enb => enb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
ena <= '1';
enb <= '1';
-- Clock process definitions
clka_process :process
begin
clka <= '0';
wait for clka_period/2;
clka <= '1';
wait for clka_period/2;
count <= count + '1';
end process;
clkb_process :process
begin
clkb <= '0';
wait for clkb_period/2;
clkb <= '1';
wait for clkb_period/2;
end process;
process
begin
wea <= "1";
web <= "0";
wait for clkb_period/2;
wea <= "0";
web <= "1";
wait for clkb_period/2;
end process;
process(clka)
begin
if clka'event and clka = '1' then
if (wea = "0") and (count < 1024) then
addra <= addra + 1 ;
end if;
dina<= dina + 1 ;
end if;
end process;
process(web)
begin
if web'event and web = "0" then
if(count >= 1024) then addrb <= addrb + 1 ; end if;
end if;
end process;
END;
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