samsung 4412 中断处理

Older versions of the ARM architecture enabled implementers considerable freedom in the design of an external interrupt controller, with no agreement over the number or types of interrupts or the software model to be used to interface to the interrupt controller block.

在外部中断控制器的设计中旧版本的ARM架构的实现能够很自由,没有在中断控制器的中断或软件模型的数量或类型限制的协议接口。

The Generic Interrupt Controller v2 (GIC) architecture provides a much moretightly controlled specification, with a greater degree of consistency between interrupt controllers from different manufacturers.

通用中断控制器 v2(GIC)体系结构提供了更严格的控制规范,以更大程度的使来自不同制造商的中断控制器之间的一致性。

This enables interrupt handler code to be more portable.

这使中断处理程序代码移植性更高。

    12.1 External interrupt requests

    12.1外部中断请求

Types of exceptionon page 11-3, described how all ARM cores have two external interrupt requests, FIQ and IRQ.

如11-3所述,所有ARM内核有两个外部中断请求FIQ和IRQ。

Both of these are level-sensitive active-LOW inputs.

这两个都是低电平有效。

Individual implementations have interrupt controllers that accept interrupt requests from a wide variety of external sources and map them onto FIQ or IRQ, causing the core to take an exception.

个人实现的中断控制器接受来自各种外部中断请求并将它们映射到FIQ或硬中断请求优先级别,导致核心带一个例外。

 In general, an interrupt exception can be taken only when the appropriate CPSR disable bit (the F and I bits respectively) is clear and if the corresponding input is asserted.

一般来说,一个中断异常可以只有当适当的CPSR禁用一些(F和我分别位)是明确的,如果相应的输入是断言。

The CPSinstruction provides a simple mechanism to enable or disable the exceptions controlled 

CPSinstruction提供了一种简单的机制来启用或禁用控制异常

by CPSR A, I and F bits (asynchronous abort, IRQ and FIQ respectively).

通过CPSR,我和F(异步中止,硬中断请求优先级别和FIQ分别)。

IEor CPS IDwill enable or disable exceptions respectively.

分别IEor CPS IDwill启用或禁用例外。

The exceptions to be enabled or disabled are specified using one or more of the letters A, I and F. Exceptions whose corresponding letters are omitted will not be modified.

启用或禁用的异常指定使用一个或多个字母A,i和f .异常的相应字母省略了不会被修改。

In Cortex-A series processors, it is possible to configure the core so that FIQs cannot be masked by software.

Cortex-A系列处理器,可以配置的核心,因此FIQs无法掩盖的软件。

This is known as Non-Maskable FIQ and is controlled by a hardware configuration input signal that is sampled when the core is reset.

这被称为屏敝FIQ由硬件配置和控制输入信号采样时,核心是重置。

They will still be masked automatically on taking an FIQ exception.

他们仍将蒙面自动FIQ例外。

    12.1.1 Assigning interrupts

    12.1.1分配中断

A system will always have an interrupt controller that accepts and arbitrates interrupts from multiple sources.

系统将总是有一个中断控制器接受来自多个来源,断定中断。

This typically contains a number of registers enabling software running on the core to mask individual interrupt sources, to acknowledge interrupts from external devices, to assign priorities to individual interrupt sources and to determine which interrupt sources are currently requesting attention or require servicing.

这通常包含许多寄存器使软件运行在核心面具个人中断源,承认从外部设备中断,将优先分配给个人中断源和确定哪些中断源目前请求关注或者需要维修。

This interrupt controller can be a design specific to the system, or it can be an implementation of the ARM Generic Interrupt Controller(GIC) architecture, described in The Generic Interrupt Controlleron page 12-7.

这个中断控制器可以设计特定的系统,也可以是一个实现手臂的通用的中断控制器(GIC)的体系结构,描述的通用的中断12-7 Controlleron页面。

    12.1.2 Simplistic interrupt handling

    12.1.2简单的中断处理

This represents the simplest kind of interrupt handler.

这是最简单的一种中断处理程序。

On taking an interrupt, additional interrupts of the same kind are disabled until explicitly enabled later.

在一个中断,中断的同样被禁用,直到显式地启用后。

We can only handle additional interrupts at the completion of the first interrupt request and there is no scope for a higher priority or more urgent interrupt to behandled during this time.

我们只能处理额外的中断在完成第一个中断请求,没有范围更高的优先级或更紧急中断behandled在这段时间。

This is not generally suitable for complex embedded systems, but it is useful to examine before proceeding to a more realistic example, in this case of a non re-entrant interrupt handler.

这不是一般适用于复杂的嵌入式系统,但它是有用的检查之前,一个更实际的例子,在这个例子中,一个非凹角中断处理程序。

The steps taken to handle aninterrupt are as follows:

处理aninterrupt采取的步骤如下:

1.An IRQ exception is raised by external hardware.

1.一个IRQ异常是由外部硬件。

The core performs several steps automatically.

核心自动执行几个步骤。

The contents of the PC inthe current execution mode are stored in LR_IRQ.

电脑在当前执行模式的内容存储在LR_IRQ。

The CPSR register is copied to SPSR_IRQ.

CPSR寄存器是SPSR_IRQ复制。

The CPSR content is updated so that the mode bits reflects the IRQ mode, and the I bit is set to mask additional IRQs.

CPSR内容中反映了IRQ模式的模式位被更新,并且 I 位设置成IRQs模式。

The PC is set to the IRQ entry in the vector table.

PC设置为IRQ向量表中的条目。

2.The instruction at the IRQ entry in the vector table (a branch to the interrupt handler) is executed.

2.IRQ矢量表中的条目的指令执行中断处理程序(分支)。

3.The interrupt handler saves the context of the interrupted program, that is, it pushes onto the stack any registers that will be corrupted by the handler.

3.中断处理程序保存中断程序的上下文中,也就是说,它推到堆栈寄存器将被处理。

These registers will be popped from stack when the handler finishes execution.

这些寄存器将从堆栈弹出当处理程序完成执行。

4.The interrupt handler determines which interrupt source must be processed and calls the appropriate device driver.

4.中断源的中断处理程序决定了必须被处理和调用适当的设备驱动程序。

5.Prepare the core to switch to previous execution state by copying the SPSR_IRQ to CPSR, and restoring the context saved earlier, and finally the PC is restored from LR_IRQ.

5.准备好的核心通过复制SPSR_IRQ CPSR 切换到先前的执行状态,并且恢复之前保存的上下文,最后PC从LR_IRQ恢复。

A very simple interrupt handler is shown in Example 12-1.

一个非常简单的中断处理程序例子 12-1所示。

-------------------------------------------------------------------------------------

IRQ_Handler

PUSH  {r0-r3, r12, lr}  @ Store AAPCS registers and LR onto the IRQ mode stack

BL @ identify_and_clear_source

BL @ C-irq_handler

POP  {r0-r3, r12, lr}  @ Restore registers and

SUBS  pc, lr, #4  @ return from exception using modified LR

-------------------------------------------------------------------------------------

    12.2 The Generic Interrupt Controller

    12.2通用中断控制器

The GIC architecture defines a Generic InterruptController (GIC) that comprises a set of hardware resources for managing interrupts in a single or multi-core system.

GIC体系结构定义了一个通用InterruptController(GIC)组成的一组硬件资源管理中断在单一或多核系统。

The GIC provides memory-mapped registers that can be used to manage interrupt sources and behavior and (in multi-core systems) for routing interrupts to individual cores.

GIC提供了内存映射寄存器,可以用来管理中断源和行为和(在多核系统)个人核心路由中断。

It enables software to mask, enable and disable interrupts from individual sources, to prioritize (in hardware) individual sources and to generate software interrupts.

它使软件面具,从个人来源、启用和禁用中断优先级(硬件)个人来源和生成软件中断。

It also provides support for the TrustZone Security Extensions described in Chapter 21 Security.

它还提供了支持TrustZone安全扩展21章中描述的安全。

The GIC accepts interrupts asserted at the system level and can signal them to each core it is connected to, potentially resulting in an IRQ or FIQ exception being taken.

GIC接受中断断言在系统水平和能信号连接到每个核心,可能导致一个IRQ或FIQ异常。

From a software perspective, a GIC has two major functional blocks:

从软件的角度来看,GIC有两个主要功能模块:

Distributor 

分配器

to which all interrupt sources in the systemare wired.

所有systemare连线中断源。

The distributor has registers to control the properties of individual interrupts such aspriority, state, security, routing information and enable status.

分配器寄存器来控制个体的属性aspriority等中断状态,安全、路由信息和启用状态。

The distributor determines which interrupt is to be forwarded to a core, through the attachedCPU interface.

分配器确定哪些中断转发到一个核心,通过attachedCPU接口。

CPU Interface 

CPU接口

through which a core receives an interrupt.

通过一个核心接收中断。

The CPU interface hosts registers to mask, identify and control states of interrupts forwarded to that core.

主机CPU接口寄存器面具,识别和控制中断的状态转发到核心。

There is a separate CPU interface for each core in the system.

有一个单独为每个核心系统中CPU接口。

Interrupts are identified in the software by a number, called an interrupt ID. An interrupt ID uniquely corresponds to an interrupt source.

中断识别软件的一个数字,称为一个中断ID。一个中断ID唯一地对应于一个中断源。

Software can use the interrupt ID to identify the source of interrupt and to invoke the corresponding handler to service the interrupt.

软件可以使用中断的中断ID来识别来源并调用相应的服务中断处理程序。

The exact interrupt ID presented to the software is determined by the system design,Interrupts can be of a number of different types:

准确的中断ID提供给软件由系统设计、中断可以许多不同的类型:

Software Generated Interrupt (SGI) 

软件生成的中断(SGI)

This is generated explicitly by software by writing to a dedicated distributor register, theSoftware Generated Interrupt Register(ICDSGIR).

这是由软件生成的显式地通过编写专门的经销商注册,软件生成的中断寄存器(ICDSGIR)。

It is most commonly used for inter-core communication.

人性讲堂是最常用的沟通。

SGIs can be targeted at all, or a selected group of cores inthe system.

可以针对所有SGIs,或一组被选的核心在系统。

Interrupt numbers 0-15 are reserved for this.

中断数0-15保留。

The exact interrupt number used for communication is at the discretion of software.

准确的中断号用于通信软件的自由裁量权。

Private Peripheral Interrupt (PPI) 

私人外设中断(PPI)

This is generated by a peripheral that isprivate to an individual core.

这是由isprivate单个核心的外围。

Interrupt numbers 16-31 are reserved for this.

中断数16-31保留。

These identify interrupt sources private to the core, and is independent of the same source on another core, for example, per-core timer.

这些中断源识别私人核心,是独立的同一来源的另一个核心,例如,每个核计时器。

Shared Peripheral Interrupt (SPI) 

共享外围中断(SPI)

This is generated by a peripheral that the Interrupt Controllercan route to more than one core.

这是由外围生成中断Controllercan途径不止一个核心。

Interrupt numbers 32-1020 are used for this.

中断使用数字32 - 1020。

SPIs are used to signal interrupts from various peripherals accessible across the whole the system.

spi用于信号从各种外设中断访问整个系统。

Interrupts can either be edge-triggered (considered to be assertedwhen the Interrupt Controller detects a rising edge on the relevant input – and to remain asserted until cleared) or level-sensitive (considered to be asserted only when the relevant input to the Interrupt Controller is HIGH).

中断可以是边沿触发(被认为是assertedwhen中断控制器检测到一个前沿的相关输入,宣称将持续到清除)或level-sensitive(被认为是断言只有当相关的中断控制器的输入是高)。

An interrupt can be in a number of different states:

一个中断可以在许多不同的部分:

• Inactive– this means that the interrupt is not asserted yet.

•活动——这意味着中断还没有断言。

• Pending– this means that the interrupt source has been asserted, but is waiting to be handled by a core.

•等待——这意味着中断源已经断言,但等待是由核心处理。

Pending interrupts are candidates to be forwarded to the CPU interface and then later on to the core.

等待中断候选人被转发到CPU接口和后来的核心。

• Active– this describes an interrupt that has been acknowledged by a core and is currently being serviced.

•积极——这描述了一个中断,承认了一个核心,目前正在维修。

• Active and pending– this describes the situation where a core is servicing the interrupt and the GIC also has a pending interrupt from the same source.

•积极和等待——这描述了情况的核心服务中断,新加坡政府投资公司也有一个等待中断从同一来源。

The priority and list of cores to which an interrupt can be delivered to are all configured in the distributor.

一个中断的优先级和内核列表可以交付给分销商都配置。

An interrupt asserted to the distributor by a peripheral will be marked in Pending state (or Active and Pending if was already Active).

一个中断断言外围的分销商将标记为挂起状态(或主动,等待如果已经主动)。

The distributor determines the highest priority pending interrupt that can be delivered to a core and forwards that to the CPU interface of the core.

经销商确定最高优先级等待中断可以送到一个核心和远期的CPU接口的核心。

At the CPU interface, the interrupt is in turn signalled to the core, at which point the core takes the FIQ or IRQ exception.

在CPU接口、中断是核心,依次表示此时核心FIQ或IRQ异常。

 The core executes the exception handler in response.

核心执行异常处理程序。

The handler must query the interrupt ID from a CPU interface register and begin servicing the interrupt source.

中断处理程序必须查询ID从CPU接口注册并开始维修中断源。

    12.2.1 Configuration

    12.2.1配置

The GIC is accessed as a memory-mapped peripheral.

GIC是访问内存映射外围。

All cores can access the common distributor block, but the CPU interface is banked, that is, each core usesthe same address to access its own private CPU interface.

所有核心可以访问常见的经销商,但CPU接口是倾斜的,也就是说,每个核心采用相同的地址来访问自己的私有CPU接口。

It is not possible for a coreto access the CPU interface of another core.

它是不可能coreto访问另一个核心的CPU接口。

See Handling interrupts in an SMP systemon page 18-14for more details.

在SMP systemon页面看到处理中断18-14for更多细节。

The distributor hosts a number of registers thatyou can use to configure the properties of individual interrupts.

经销商主机的注册你可以使用配置属性的个人中断。

These configurable properties are:

这些可配置属性:

• An interrupt priority.

•一个中断优先级。

The distributor uses this to determine which interrupt is next forwarded to the CPU interface.

中断的经销商使用这个来确定下一个转发到CPU接口。

• An interrupt configuration.

•一个中断配置。

This determines if an interrupt is level- or edge-sensitive.

这决定了如果一个中断或edge-sensitive水平。

• An interrupt target.

•一个中断的目标。

This determines a list of cores to which an interrupt can be forwarded.

这决定了核心的列表可以转发一个中断。

• Interrupt enable or disable status.

•中断启用或禁用状态。

Only those interrupts that are enabled in the distributor are eligible to be forwarded when they become pending.

只有那些中断中启用的分销商资格被转发时变得悬而未决。

• Interrupt security determines whether the interrupt is allocated to Secure or Normal world software.

•中断安全决定中断分配给软件安全或正常的世界。

• An Interrupt state.

•一个中断状态。

The distributor also provides priority masking by which interrupts below a certain priority are prevented from reaching the core.

分配器还提供优先级屏蔽，低于一定的优先级的中断是无法到达核心的。

The distributor uses this when determining whether a pending interrupt can be forwarded to a particular core.

分配器使用这个决定推迟中断时可以转发到一个特定的核心。

The CPU interfaces on each core helps with fine-tuning interrupt control and handling on that core:

在内核中每个核心的CPU接口有助于修正中断的控制和处理:

12.2.2 Initialization

12.2.2初始化

Both the distributor and the CPU interfaces are disabled at reset.

经销商和CPU接口在重置禁用。

The GIC must be initialized after reset before it can deliver interrupts to the core.

新加坡政府投资公司必须初始化复位后才能交付核心中断。

 In the distributor, software must configure the priority, target, security and enable individual interrupts.

软件必须配置优先级经销商,目标,安全,使个人的中断。

The distributor block must subsequently be enabled through its control register.

经销商块随后必须通过其控制寄存器。

For each CPU interface, software must program the priority mask and preemption settings.

为每个CPU接口,软件必须程序优先面具和抢占设置。

 Each CPU interface block itself must be enabled through its control register.

每个CPU接口块本身必须启用通过其控制寄存器。

This prepares the GIC to deliver interrupts to the core.

这个准备GIC将中断。

Before interrupts are expected inthe core, software prepares the core to take interrupts by setting a valid interrupt vector in the vector table, and clearing interrupt masks bits in the CPSR.

中断之前预计在核心,核心软件准备采取中断矢量表中通过设置一个有效的中断向量,并清除中断CPSR面具碎片。

The entire interrupt mechanism in the system can be disabled by disabling the distributor block.

整个系统中的中断机制可以通过禁用分销商的块被禁用。

 Interrupt delivery to an individualcore can be disabled by disabling its CPU interface block, or by setting mask bits in CPSR of that core.

可以禁用中断交付一个individualcore禁用其CPU接口块,或通过设置掩码位CPSR的核心。

Individual interrupts can also be disabled (or enabled) in the distributor.

个人也可以禁用中断(或启用)分销商。

For an interrupt to reach the core, the individual interrupt, distributor and CPU interface must all be enabled, and the CPSR interrupt mask bits cleared.

一个中断到达核心,个人中断,分销商和CPU接口都必须被启用,和CPSR中断屏蔽位清除。

    12.2.3 Interrupt handling

    12.2.3中断处理

When the core takes an interrupt, it jumps to the top-level interrupt vector obtained from the vector table and begins execution.

核心需要一个中断时,跳转到中断向量的向量顶级表并开始执行。

The top-level interrupt handler reads the Interrupt Acknowledge Registerfrom the CPU Interface block to obtain the interrupt ID.As well as returning the interrupt ID, the read causes the interrupt to be marked as active in the distributor.

顶级中断处理程序读取中断承认Registerfrom CPU接口块获取中断ID.As中断返回ID,阅读使中断标记为活跃的分销商。

Once the interrupt ID is known (identifying the interrupt source), the top-level handler can now dispatch a device-specific handler to service the interrupt.

一旦中断ID是已知的(确定中断源),顶级处理器可以派遣一个特定于设备的处理程序服务中断。

 When the device-specific handler finishes execution, the top-level handler writes the same 

特定于设备的处理程序执行完成时,高层处理程序写相同的

interrupt ID to the End of Interrupt register in the CPU Interface block, indicating the end of 

中断ID的中断寄存器在CPU接口,表示结束

interrupt processing.

中断处理。

Apart from removing the active status, which will make the final interrupt status either Inactive, or Pending (if the state was Active and Pending), this will enable the CPU Interface to forward more pending interrupts to the core.

除了删除活动状态,这将使最终的中断状态不活跃,或等待(如果国家活跃和等待),这将使CPU接口转发更多等待中断的核心。

This concludes the processing of a single interrupt.

这就是一个中断的处理。

It is possible for there to be more than one interrupt waiting to be serviced on the same core, but the CPU Interface can signalonly one interrupt at a time.

有可能有多个中断等待服务相同的核心,但CPU接口可以signalonly中断一次。

The top-level interrupt handler repeats the above sequence until it reads the special interrupt ID value 1023, indicating that there are no more interrupts pending at this core.

顶级中断处理程序重复上述序列,直到1023年它读取特殊中断ID值,表明没有中断等待在这个核心。

This special interrupt ID is called the spurious interrupt ID. The spurious interrupt ID is a reserved value, and cannot be assigned to any device in the system.

这种特殊的中断ID被称为伪中断ID。伪中断ID是一个保留价值,并且不能分配给系统中任何设备。

When the top-level handler has read the spurious interrupt ID it can complete its execution, and prepare the core to resume the task it was doing before taking the interrupt.

当顶级处理器读过伪中断ID可以完成其执行,并准备简历的核心任务是做之前中断。