我的BIOS之行（1）-CPU Introduction & Multi-Processor

前言

想对自己在本月所学的东西做一个总结，因而产生了写本系列博客的冲动，由于工作较为繁忙，不能及时更新，敬请原谅

CPU Introduction & Multi-Processor

本节博客将简单介绍CPU的情况。

1、CPU简介

CPU – The Central Processor Unit is the hardware within a computer system which carries out the instructions of a computer program by performing the basic arithmetical, logical, and input/output operations of the system.

CPU是运算的中心处理，相当于计算机的大脑，在计算机中起到至关重要的作用。

Two typical components of a CPU are the arithmetic logic unit (ALU), which performs arithmetic and logical operations, and the control unit (CU), which extracts instructions from memory and decodes and executes them, calling on the ALU when necessary.

CPU典型组件有ALU（算术逻辑单元）与CU（控制单元）

CPU中的寄存器如下：

1.1CPU Pipeline

Pipeline : An instruction pipeline is a technique used in the design of computers to increase their instruction throughput (the number of instructions that can be executed in a unit of time). Pipelining does not reduce the time to complete an instruction, but increases the number of instructions that can be processed at once.

Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock cycle (the green column), the earliest instruction is in MEM stage, and the latest instruction has not yet entered the pipeline.

其实通过这张图就可以看到基础的5级流水线制的基础运行模式！IF=指令取出,ID=指令解码,EX=执行,MEM =内存访问,WB=寄存器会写)。第四时钟周期(绿色列),MEM阶段,最早的指令和最新指令尚未进入管道。

BSP : The Boot Strap Processor is responsible for initializing the system and for booting the operating system.

AP : The Application processors are activated only after the operating system is up and running.

APIC : The Advanced Programmable Interrupt Controller units are collectively responsible for delivering interrupts from interrupt sources to interrupt destinations throughout the multiprocessor system.

具体可以参考计算机组成原理这本书

未完待续

主要是对计算机组成的介绍，因此我在此并不多想在这个地方划给太多的时间，今天暂时整理到这里！