NES 6502
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.686 ; create 32 bit code.mmx.xmm .model flat, stdcall ; 32 bit memory modeloption casemap :none ; case sensitive; ===========================================================================;;;;this source is based on VirtuaNES && (\virtuanessrc097\NES\Cpu.cpp);nesterJ && (nesterj_0_51_05_src\gui\SRC\NES\CPU\Nes6502.c);C/CPP into ASM by xuling ;;; 2A03 Instruction comment from nesdev.com (nesdev_weekly\www\6502.txt);;;; ===========================================================================;=======================; Interrupt ;=======================NMI_VECTORequ FFFAh; nmi RES_VECTORequ FFFCh; resetIRQ_VECTORequ FFFEh; irq NMI_FLAGequ 2; nmi interrupt pending flagIRQ_FLAGequ 1; irq interrupt pending flag ;=======================; Pro Status ;=======================C_FLAGequ 01h; 1: carryZ_FLAGequ 02h; 1: zero I_FLAGequ 04h; 1: intterrupt enable D_FLAGequ 08h; 1: dec mode nes did not use this modeB_FLAGequ 10h; 1: software intterrupt flag R_FLAGequ 20h; 1: this flag is reservedV_FLAGequ 40h; 1: overflow flagN_FLAGequ 80h; 1: negative flag INT_C equ 7DUMMY_SBC_V_TEST equ 0byt equ byte ptrwot equ word ptrdwot equ dword ptr $aequ dword ptr[edi] ; 0$x equ dword ptr[edi+4] ; 1$yequ dword ptr[edi+8] ; 2$sequ dword ptr[edi+12] ; 3$pequ dword ptr[edi+16] ; 4$pcequ dword ptr[edi+20] ; 5$dmaequ dword ptr[edi+24] ; 6$dis equ dword ptr[edi+28] ; 7$t1equ dword ptr[edi+32] ; 8ALIGNXMMequ align 16;=======================; extern symbols ;=======================extrn nes_Read@4:procextrn nes_Write@8:procextrn nes_Readw@4:procextrn ram:farextrn regs:farextrn zn_Table:farextrn dma_Cycles:farextrn cpu_banks:farextrn int_Pending:far;===================; Function ;===================.codeexec2a03 proc C option prologue:none, epilogue:none push ebx ;U - save old framepushesi ;V - save old frame pushedi ;U - save old framepushebp ;V - save old frame ; esi edi ebx ebp unscratch regs we can use this to do useful things; eax ecx edx scratch regs to do logic opr use completion can be discarded; ebx <- save now P (nes's PSW reg); ebp <- save exec Cycles counter ; esi <- save now PC (nes's EIP reg); edi <- save regs rootlea edi, regs ;U - ebx <- save regs root moveax, dwot[esp+20];V - /N load dispatch Cycles-> arg1 xorebp, ebp ;U - reset Cycles counter mov$dis, eax ;V - write back adjacent mem reduce cache pollutemovesi, $pc ;U - load PC mov ebx, $p ;V - load P ALIGNXMM ; align main_Loop:moveax, $dis ;U - load dispatch Cyclesmovedx, ebp ;V - copy Now Cycles countermovecx, $dma ;U - /N load now DMA Cycles movebp, edx ;V - cmpeax, edx ;U - dispatch Cycles > Cycles counter ?jgdo_DMA_test ;V - TRUE:remain Cycles alive do DMA test FALSE:remain burning out moveax, ebp ;U - return now Cycles counter movecx, edx ;V - mov$pc, esi ;U - write back PC mov $p, ebx ;V - write back Ppopebp ;U - thaw old framepopedi;V - thaw old framepopesi ;U - thaw old framepopebx;V - thaw old frameret ;N - proc ret ...ALIGNXMMdo_DMA_test:test ecx, ecx ;U - DMA Cycles active ?je dec_Begin ;V - TRUE calc Cycles FALSE:immed decode sub eax, edx ;U - remain Cycleslea edi, [edi];V - cmp ecx, eax ;U - cmp DMA Cycles/remain Cycles jge remain_Out;V - TRUE:remain Cycles burning out FALSE: DMA Cycles burning outadd ebp, ecx ;U - dma buring out mov $dma, 0 ;V - reset DMA Cyclesleaeax, [eax];U - jmp dec_Begin ;V - jmp decode ... short jmp ALIGNXMMremain_Out:subecx, eax ;U - remain cycles buring out mov eax, $dis;V - Cycles just enoughmov $dma,ecx ;U - write back DMA Cyclesmov$pc, esi ;U - write back PC mov $p, ebx ;V - write back Ppopebp ;U - thaw old framepopedi;V - thaw old framepopesi ;U - thaw old framepopebx;V - thaw old frameret ;N - proc ret ...ALIGNXMMdec_Begin:mov eax, esi ;U - load PC inc esi ;V - ++ PC mov edx, eax ;U - copy PC and eax, 0FFFFh;V - limit bits shr eax, 13 ;U - get Bank ID and edx, 01FFFh;V - Bank's interval mov ecx, dwot[cpu_banks+eax*4];U - get Bank IDlea edx, [edx] ;V - movzx eax, byt[ecx+edx];N - get PC's val lea edx, [edx+ecx+1] ;U - next addr index jmp [OPTAB+eax*4] ;V - /N short/far jmp ;***;ADC ; 69: #$2 cycles;65: ZERO PAGE3 cycles;75: ZERO PAGE X 4 cycles;6D: ABS 4 cycles;07Dh: ABS X 4 cycles (crossing page ++ cycles);79: ABS Y 4 cycles (crossing page ++ cycles);61: X INDIRECT 6 cycles;71: INDIRECT Y 4 cycles (crossing page ++ cycles);Algorithm: ;; unsigned int temp = src + AC + (IF_CARRY() ? 1 : 0);; SET_ZERO(temp & 0xff);/* This is not valid in decimal mode */; if (IF_DECIMAL()) {; if (((AC & 0xf) + (src & 0xf) + (IF_CARRY() ? 1 : 0)) > 9) {;temp += 6;;};SET_SIGN(temp);;SET_OVERFLOW(!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));;if (temp > 0x99) {;temp += 96;;};SET_CARRY(temp > 0x99);; } else {;SET_SIGN(temp);;SET_OVERFLOW(!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));;SET_CARRY(temp > 0xff);; }; AC = ((BYTE) temp);;*************************************************OP69: ; ADC #$ 2 cyclesmovzxecx,byt[edx];N - load #$ movzxeax,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags leaesi,[esi+1];V - ++ PC shrebx,1;U - with C leaebp,[ebp+2];V - 2 Cycles adcal,cl;U - ADC movdl,dl;V - seto cl ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl ecx,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+eax*4];V - reset Z-N Flags orebx,ecx ;U - reset V Flag mov$a,eax;V - write Back REG A jmpPollInt;N - ... OP65: ; ADC ZERO PAGE 3 cycles movzxeax,byt[edx];N - load addr8Real movzxecx,byt[ram+eax];N - load addr8Real's VAL movzxeax,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags leaesi,[esi+1];V - ++ PC shrebx,1;U - with C leaebp,[ebp+3];V - 3 Cycles adcal,cl;U - ADC movdl,dl;V - seto cl ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl ecx,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+eax*4];V - reset Z-N Flags orebx,ecx;U - reset V Flag mov$a,eax;V - write Back REG A jmpPollInt;N - ... OP75: ; ADC ZERO PAGE X 4 cyclesmovzxeax,byt[edx];N - load addr8Temp addal,byt[edi+4];U - get addr8Realmovbl,bl;V - movzxecx,byt[ram+eax];N - load addr8Real's VAL movzxeax,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags leaesi,[esi+1];V - ++ PC shrebx,1;U - with C leaebp,[ebp+4];V - 4 Cycles adcal,cl;U - ADC movdl,dl;V - seto cl ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl ecx,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+eax*4];V - reset Z-N Flags orebx,ecx;U - reset V Flag mov$a,eax;V - write Back REG A jmpPollInt;N - ... OP6D: ; ADC ABS 4 cycles movax,wot[edx];U - load addr16Real addsi,2;V - ++ PC pusheax;U - PUSH addr16Realleaebp,[ebp+4];V - 4 Cyclescallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags andeax,0FFh;V - limit Bits shrebx,1;U - with C movebp,ebp;V - adccl,al;U - ADC movdl,dl;V - seto al ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP7D: ; ADC ABS X 4 cycles (corssing page)movzxeax,wot[edx];N - load addr16Tempmovzxecx,byt[edi+4];N - load REG X addecx,eax;U - ABS X leaesi,[esi+2];V - ++ PC andbl,00111101b;U - clr N-V-Z Flagssubah,ch;V - test CrossPage adcebp,4 ;U - 4/5 Cycles pushecx;V - PUSH addr16Realcallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits movedx,edx;V - shrebx,1;U - with C movebx,ebx;V - adccl,al;U - ADC movdl,dl;V - seto al ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP79: ; ADC ABS Y 4 cycles (corssing page)movzxeax,wot[edx];N - load addr16Tempmovzxecx,byt[edi+8];N - load REG Yaddecx,eax;U - ABS Yleaesi,[esi+2];V - ++ PC andbl,00111101b;U - clr N-V-Z Flagssubah,ch;V - test CrossPage adcebp,4 ;U - 4/5 Cycles pushecx;V - PUSH addr16Realcallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits movedx,edx;V - shrebx,1;U - with C movebx,ebx;V - adccl,al;U - ADC movdl,dl;V - seto al ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP61: ; ADC X INDIRECT 6 cyclesmovzxeax,byt[edx];N - load addr8Tempaddal,byt[edi+4];U - X INDIRECT andbl,00111101b;V - clr N-V-Z Flagsmovcx,wot[eax+ram];U - get addr16Realaddbp,6;V - 6 Cycles pushecx;U - PUSH addr16Realleaesi,[esi+1];V - ++ PC callnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits movedx,edx;V - shrebx,1;U - with C movebx,ebx;V - adccl,al;U - ADC movdl,dl;V - seto al ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP71: ; ADC INDIRECT Y movzxedx,byt[edx];N - load addr8Realmovzxeax,wot[edx+ram];N - load addr16Tempmovzxecx,byt[edi+8];N - load REG Yaddecx,eax;U - ABS Yleaesi,[esi+1];V - ++ PC andbl,00111101b;U - clr N-V-Z Flagssubah,ch;V - test CrossPage adcebp,4 ;U - 4/5 Cycles pushecx;V - PUSH addr16Realcallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits movedx,edx;V - shrebx,1;U - with C movebx,ebx;V - adccl,al;U - ADC movdl,dl;V - seto al ;N - SETcc set O flag rcl ebx, 1 ;N - C Flag into NES's Flag REG shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... ;***;SBC ;EB: #$2 cycles (unofficial); E9: #$2 cycles;E5: ZERO PAGE3 cycles;F5: ZERO PAGE X 4 cycles;ED: ABS 4 cycles;FD: ABS X 4 cycles (crossing page ++ cycles);F9: ABS Y 4 cycles (crossing page ++ cycles);E1: X INDIRECT 6 cycles;F1: INDIRECT Y 4 cycles (crossing page ++ cycles);Algorithm:;; unsigned int temp = AC - src - (IF_CARRY() ? 0 : 1);;SET_SIGN(temp);;SET_ZERO(temp & 0xff);/* Sign and Zero are invalid in decimal mode */;SET_OVERFLOW(((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));;if (IF_DECIMAL()) {;if ( ((AC & 0xf) - (IF_CARRY() ? 0 : 1)) < (src & 0xf)) /* EP */ {;temp -= 6;;};if (temp > 0x99) {;temp -= 0x60;;};};SET_CARRY(temp < 0x100);;AC = (temp & 0xff);;*************************************************OPE9: ; SBC #$ 2 cycles movzxecx,byt[edx];N - load #$ movzxeax,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags leaesi,[esi+1];V - ++ PC xorebx,1 ;U - NEG C moveax,eax;V - shrebx,1;U - with C leaebp,[ebp+2];V - 2 Cycles sbbal,cl;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto cl ;N - SETcc set O flag ELSEsetno cl ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl ecx,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+eax*4];V - reset Z-N Flags orebx,ecx ;U - reset V Flag mov$a,eax;V - write Back REG A jmpPollInt;N - ... OPE5: ; SBC ZERO PAGE 3 cycles movzxecx,byt[edx];N - load addr8Real movzxecx,byt[ram+ecx];N - load VAL movzxeax,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags leaesi,[esi+1];V - ++ PC xorebx,1 ;U - NEG C moveax,eax;V - shrebx,1;U - with C leaebp,[ebp+3];V - 3 Cycles sbbal,cl;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto cl ;N - SETcc set O flag ELSEsetno cl ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl ecx,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+eax*4];V - reset Z-N Flags orebx,ecx ;U - reset V Flag mov$a,eax;V - write Back REG A jmpPollInt;N - ... OPF5: ; SBC ZERO PAGE X 4 cyclesmovzxecx,byt[edx];N - load addr8Real addcl,byt[edi+4];U - ZERO PAGE X movdl,dl;V - movzxecx,byt[ram+ecx];N - load VAL movzxeax,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags leaesi,[esi+1];V - ++ PC xorebx,1 ;U - NEG C moveax,eax;V - shrebx,1;U - with C leaebp,[ebp+4];V - 4 Cycles sbbal,cl;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto cl ;N - SETcc set O flag ELSEsetno cl ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl ecx,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+eax*4];V - reset Z-N Flags orebx,ecx ;U - reset V Flag mov$a,eax;V - write Back REG A jmpPollInt;N - ... OPED: ; SBC ABS 4 cycles movax,wot[edx];U - load addr16Real addsi,2;V - ++ PC pusheax;U - PUSH addr16Realleaebp,[ebp+4];V - 4 Cyclescallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andebx,00111101b;U - clr N-V-Z Flags andeax,0FFh;V - limit Bits xorebx,1 ;U - NEG C moveax,eax;V - shrebx,1;U - with C movebp,ebp;V - sbbcl,al;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto al ;N - SETcc set O flag ELSEsetno al ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OPFD: ; SBC ABS X 4 cycles (corssing page)movzxeax,wot[edx];N - load addr16Tempmovzxecx,byt[edi+4];N - load REG X addecx,eax;U - ABS X leaesi,[esi+2];V - ++ PC andbl,00111101b;U - clr N-V-Z Flagssubah,ch;V - test CrossPage adcebp,4 ;U - 4/5 Cycles pushecx;V - PUSH addr16Realcallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits xorebx,1 ;V - NEG C shrebx,1;U - with C movebx,ebx;V - sbbcl,al;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto al ;N - SETcc set O flag ELSEsetno al ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OPF9: ; SBC ABS Y 4 cycles (corssing page)movzxeax,wot[edx];N - load addr16Tempmovzxecx,byt[edi+8];N - load REG Yaddecx,eax;U - ABS Yleaesi,[esi+2];V - ++ PC andbl,00111101b;U - clr N-V-Z Flagssubah,ch;V - test CrossPage adcebp,4 ;U - 4/5 Cycles pushecx;V - PUSH addr16Realcallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits xorebx,1 ;V - NEG C shrebx,1;U - with C movebx,ebx;V - sbbcl,al;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto al ;N - SETcc set O flag ELSEsetno al ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OPE1: ; SBC X INDIRECT movzxeax,byt[edx];N - load addr8Tempaddal,byt[edi+4];U - X INDIRECT andbl,00111101b;V - clr N-V-Z Flagsmovcx,wot[eax+ram];U - get addr16Realaddbp,6;V - 6 Cycles pushecx;U - PUSH addr16Realleaesi,[esi+1];V - ++ PC callnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits xorebx,1 ;V - NEG C shrebx,1;U - with C movebx,ebx;V - sbbcl,al;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto al ;N - SETcc set O flag ELSEsetno al ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OPF1: ; SBC INDIRECT Y movzxedx,byt[edx];N - load addr8Realmovzxeax,wot[edx+ram];N - load addr16Tempmovzxecx,byt[edi+8];N - load REG Yaddecx,eax;U - ABS Yleaesi,[esi+1];V - ++ PC andbl,00111101b;U - clr N-V-Z Flagssubah,ch;V - test CrossPage adcebp,4 ;U - 4/5 Cycles pushecx;V - PUSH addr16Realcallnes_Read@4;N - call PROC movzxecx,byt[edi];N - load REG A andeax,0FFh;U - limit Bits xorebx,1 ;V - NEG C shrebx,1;U - with C movebx,ebx;V - sbbcl,al;U - SBC movdl,dl;V - IFDEF DUMMY_SBC_V_TESTseto al ;N - SETcc set O flag ELSEsetno al ;N - SETcc set O flag ENDIF rcl ebx, 1 ;N - C Flag into NES's Flag REG xorebx,1 ;U - NEG C moveax,eax ;V - shl eax,6;U - reset pos (ready to NES's V Flag)orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags orebx,eax;U - reset V Flag mov$a,ecx;V - write Back REG A jmpPollInt;N - ...;***;DEC ;C6: ZERO PAGE5 cycles;D6: ZERO PAGE X 6 cycles;CE: ABS 6 cycles;DE: ABS X 7 cycles ;XCA: REG2 cycles;Y 88: REG2 cycles;Algorithm:;; src = (src - 1) & 0xff;; SET_SIGN(src);; SET_ZERO(src);; STORE(address, (src));;*************************************************OPC6: ; DEC ZERO PAGE 5 Cycles movzx eax, byt[edx];N - eax <- a8Real movzxecx,byt[ram+eax];N - ecx <- MEM dececx;U - DEC leaesi,[esi+1];V - ++ PC and ecx, 0FFh ;U - leaebp,[ebp+5];V - 5 Cycles movbyt[ram+eax],cl;U - MEM <- ecx andbl,07Dh;V - clr Z-N orebx,dwot[zn_Table+ecx*4];U - set Z-NjmpPollInt;N - OPD6: ; DEC ZERO PAGE X 6 cycles movzx eax, byt[edx];N - eax <- a8Temp add al, byt[edi+4];U - eax <- a8Real movdl, dl ;V - movzxecx,byt[ram+eax];N - ecx <- MEM dececx;U - DEC leaesi,[esi+1];V - ++ PC and ecx, 0FFh ;U - leaebp,[ebp+6];V - 6 Cycles movbyt[ram+eax],cl;U - MEM <- ecx andbl,07Dh;V - clr Z-N orebx,dwot[zn_Table+ecx*4];U - set Z-NjmpPollInt;N - OPCE: ; DEC ABS 6 cyclesmovzxecx,wot[edx];N - load addr16Real pushecx;U - ready addr16Real<-nes_Read's arg mov$t1,ecx;V - save old framecallnes_Read@4;N - call nes_Read@4deceax;U - DEC OPR andebx,07Dh;V - clr Z-N Flags pusheax;U - arg2push$t1;V - arg1 andeax,0FFh;U - limit Bits leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags leaebp,[ebp+6];V - 6 Cycles callnes_Write@8;N - call nes_Write@8jmpPollInt;N - ...OPDE: ; DEC ABS X 7 cyclesmovzxecx,wot[edx];N - load addr16Tempmovzxeax,byt[edi+4];N - load REG X movebx,ebx;U - addecx,eax;V - ABS X get addr16Realpushecx;U - ready addr16Real<-nes_Read's arg mov$t1,ecx;V - save old framecallnes_Read@4;N - call nes_Read@4deceax;U - DEC OPR andebx,07Dh;V - clr Z-N Flags pusheax;U - arg2push$t1;V - arg1 andeax,0FFh;U - limit Bits leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags leaebp,[ebp+7];V - 7 Cycles callnes_Write@8;N - call nes_Write@8jmpPollInt;N - ...OPCA: ; DEX 2 cycles moveax,$x;U - load REG X leaebp,[ebp+2];V - 2 Cycles deceax;U - DEC OPR andebx,07Dh;V - clr Z-N Flags mov$x,eax;U - write REG X andeax,0FFh;V - limit Bits orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags jmpPollInt;V - /N ...OP88: ; DEY moveax,$y;U - load REG Yleaebp,[ebp+2];V - 2 Cycles deceax;U - DEC OPR andebx,07Dh;V - clr Z-N Flags mov$y,eax;U - write REG Yandeax,0FFh;V - limit Bits orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags jmpPollInt;V - /N ...;***;INC ;E6: ZERO PAGE5 cycles;F6: ZERO PAGE X 6 cycles;EE: ABS 6 cycles;FE: ABS X 7 cycles ;XE8: REG2 cycles;YC8: REG2 cycles;Algorithm:;; src = (src + 1) & 0xff;; SET_SIGN(src);; SET_ZERO(src);; STORE(address, (src));;*************************************************OPE6: ; INC ZERO PAGE 5 cyclesmovzx eax, byt[edx];N - load ZeroPage Index movzxecx,byt[ram+eax];N - load From MEM ->inccl;U - INC OPR movebx,ebx;V - movecx,ecx;U - leaesi,[esi+1];V - ++ PC movbyt[ram+eax],cl;U - write Back MEM <-andbl,07Dh;V - clr Z-N Flags leaebp,[ebp+5];U - 5 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;N - ... OPF6: ; INC ZERO PAGE X 6 cyclesmovzx eax, byt[edx];N - load ZeroPage Index addal,byt[edi+4];U - ZERO PAGE X movbl,bl;V - movzxecx,byt[ram+eax];N - load From MEM ->inccl;U - INC OPR movebx,ebx;V - movecx,ecx;U - leaesi,[esi+1];V - ++ PC movbyt[ram+eax],cl;U - write Back MEM <-andbl,07Dh;V - clr Z-N Flags leaebp,[ebp+6];U - 6 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;N - ... OPEE: ; INC ABS 6 cyclesmovzxecx,wot[edx];N - load addr16Real pushecx;U - ready addr16Real<-nes_Read's arg mov$t1,ecx;V - save old framecallnes_Read@4;N - call nes_Read@4inceax;U - INC OPR andebx,07Dh;V - clr Z-N Flags pusheax;U - arg2push$t1;V - arg1 andeax,0FFh;U - limit Bits leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags leaebp,[ebp+6];V - 6 Cycles callnes_Write@8;N - call nes_Write@8jmpPollInt;N - ...OPFE: ; INC ABS X 7 cycles movzxecx,wot[edx];N - load addr16Tempmovzxeax,byt[edi+4];N - load REG X movebx,ebx;U - addecx,eax;V - ABS X get addr16Realpushecx;U - ready addr16Real<-nes_Read's arg mov$t1,ecx;V - save old framecallnes_Read@4;N - call nes_Read@4inceax;U - INC OPR andebx,07Dh;V - clr Z-N Flags pusheax;U - arg2push$t1;V - arg1 andeax,0FFh;U - limit Bits leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags leaebp,[ebp+7];V - 7 Cycles callnes_Write@8;N - call nes_Write@8jmpPollInt;N - ...OPE8: ; INX moveax,$x;U - load REG X leaebp,[ebp+2];V - 2 Cycles inceax;U - INC OPR andebx,07Dh;V - clr Z-N Flags mov$x,eax;U - write REG X andeax,0FFh;V - limit Bits orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags jmpPollInt;V - /N ...OPC8: ; INY moveax,$y;U - load REG Yleaebp,[ebp+2];V - 2 Cycles inceax;U - INC OPR andebx,07Dh;V - clr Z-N Flags mov$y,eax;U - write REG Yandeax,0FFh;V - limit Bits orebx,dwot[zn_Table+eax*4] ;U - reset Z-N Flags jmpPollInt;V - /N ...;***;CMP ; C9: #$2 cycles;C5: ZERO PAGE3 cycles;D5: ZERO PAGE X 4 cycles;CD: ABS 4 cycles;DD: ABS X 4 cycles (crossing page ++ cycles);D9: ABS Y 4 cycles (crossing page ++ cycles);C1: X INDIRECT 6 cycles;D1: INDIRECT Y 5 cycles (crossing page ++ cycles);XE0: #$2 cycles;X E4: ZERO PAGE 3 cycles ;X EC: ABS4 cycles ;YC0:#$2 cycles;YC4: ZERO PAGE3 cycles;YCC: ABS4 cycles;;Algorithm:;; src = AC - src;; SET_CARRY(src < 0x100);; SET_SIGN(src);; SET_ZERO(src &= 0xff);;*************************************************; =====;A; =====OPC9: ; CMP #$ 2 cyclesmovcl,byt[edx] ;U - ecx <- MEM moval,byt[edi];V - eax <- A andbl,01111100b;U - clr Z-N-Csubal, cl;V - CMP setnc cl ;N - get C leaebp,[ebp+2];U - 2 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,ecx;U - set C jmpPollInt;V - /N ...OPC5: ; CMP ZERO PAGE 3 cycles movzxecx,byt[edx] ;N - ecx <- a8Real movcl, byt[ram+ecx];U - ecx <- MEM moval,byt[edi];V - eax <- A andbl,01111100b;U - clr Z-N-Csubal, cl;V - CMP setnc cl ;N - get C leaebp,[ebp+3];U - 3 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,ecx;U - set C jmpPollInt;V - /N ...OPD5: ; CMP ZERO PAGE X 4 cyclesmovzxecx,byt[edx];N - ecx <- a8Temp addcl,byt[edi+4];U - ecx <- a8Real moval,al;V - movdl,byt[ram+ecx];U - edx <- MEM moval,byt[edi];V - eax <- A andbl,01111100b;U - clr Z-N-C subal, dl;V - CMP setnc dl ;N - leaebp,[ebp+4];U - 4 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,edx;U - set C jmpPollInt;V - /N ...OPCD: ; CMP ABS 4 cycles movax,wot[edx];U - eax <- a16Real addsi,2;V - ++ PC pusheax;U - leaebp,[ebp+4];V - 4 Cyclescallnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi];V - ecx <- A subcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...OPDD: ; CMP ABS X (test cross page)movzxecx, byt[edi+4];N - ecx <- X movzxeax,wot[edx];U - eax <- a16Temp addecx, eax ;U -leaesi, [esi+2];V - ++ PC pushecx ;U - movesi, esi ;V -sub ah,ch ;U - movdh,dh;V - adc ebp, 4 ;U - 4/5 Cyclesmoveax, eax ;V - callnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi];V - ecx <- A subcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...OPD9: ; CMP ABS Y (test cross page)movzxecx, byt[edi+8];N - ecx <- Y movzxeax,wot[edx];U - eax <- a16Temp addecx, eax ;U -leaesi, [esi+2];V - ++ PC pushecx ;U - movesi, esi ;V -sub ah,ch ;U - movdh,dh;V - adc ebp, 4 ;U - 4/5 Cyclesmoveax, eax ;V - callnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi];V - ecx <- A subcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...OPC1: ; CMP X INDIRECT 6 cycles movzxeax,byt[edx];N - eax <- a8Temp addal,byt[edi+4];U - eax <- a8Realmovbl,bl ;V - movzxeax,wot[ram+eax];N - leaesi, [esi+1];U - ++ PC movebx, ebx ;V - pusheax;U - leaebp,[ebp+6];V - 6 Cyclescallnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi];V - ecx <- A subcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...OPD1: ; CMP INDIRECT Y (test cross page)movzxecx, byt[edi+8];N - ecx <- Y movzxeax,byt[edx];N - eax <- a8Realmovzx eax, wot[ram+eax];N - eax <- a16Real addecx, eax ;U -leaesi, [esi+1];V - ++ PC pushecx ;U - movesi, esi ;V -sub ah,ch ;U - movdh,dh;V - adc ebp, 5 ;U - 5/6 Cyclesmoveax, eax ;V - callnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi];V - ecx <- A subcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...; =====;X; =====OPE0: ; CPX #$ movcl,byt[edx] ;U - ecx <- MEM moval,byt[edi+4];V - eax <- Xandbl,01111100b;U - clr Z-N-Csubal, cl;V - CMP setnc cl ;N - get C leaebp,[ebp+2];U - 2 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,ecx;U - set C jmpPollInt;V - /N ...OPE4: ; CPX ZERO PAGE movzxecx,byt[edx] ;N - ecx <- a8Real movcl, byt[ram+ecx];U - ecx <- MEM moval,byt[edi+4];V - eax <- X andbl,01111100b;U - clr Z-N-Csubal, cl;V - CMP setnc cl ;N - get C leaebp,[ebp+3];U - 3 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,ecx;U - set C jmpPollInt;V - /N ...OPEC: ; CPX ABS movax,wot[edx];U - eax <- a16Real addsi,2;V - ++ PC pusheax;U - leaebp,[ebp+4];V - 4 Cyclescallnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi+4];V - ecx <- X subcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...; =====;y; =====OPC0: ; CPY #$ movcl,byt[edx] ;U - ecx <- MEM moval,byt[edi+8];V - eax <- Y andbl,01111100b;U - clr Z-N-Csubal, cl;V - CMP setnc cl ;N - get C leaebp,[ebp+2];U - 2 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,ecx;U - set C jmpPollInt;V - /N ...OPC4: ; CPY ZERO PAGE movzxecx,byt[edx] ;N - ecx <- a8Real movcl, byt[ram+ecx];U - ecx <- MEM moval,byt[edi+8];V - eax <- Y andbl,01111100b;U - clr Z-N-Csubal, cl;V - CMP setnc cl ;N - get C leaebp,[ebp+3];U - 3 Cycles andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+1];V - ++ PC orebx,ecx;U - set C jmpPollInt;V - /N ...OPCC: ; CPY ABS movax,wot[edx];U - eax <- a16Real addsi,2;V - ++ PC pusheax;U - leaebp,[ebp+4];V - 4 Cyclescallnes_Read@4;N - andbl,01111100b;U - clr Z-N-C movcl,byt[edi+8];V - ecx <- Ysubcl, al;U - CMP movdl,dl;V - setnc al ;N - SETcc orebx,eax;U - set C andecx,0FFh;V - orebx,dwot[zn_Table+ecx*4] ;U - set Z-N jmpPollInt;V - /N ...OP90: ; BCC C clr JMPtest ebx, 00000001bje Fhitjmp FnhitOPD0: ; BNE Z clr JMP test ebx, 00000010bje Fhitjmp FnhitOP10: ; BPL N clr JMPtest ebx, 10000000bje Fhitjmp FnhitOP50: ; BVC V clr JMPtest ebx, 01000000bje Fhitjmp FnhitOPB0: ; BCS C set JMPtest ebx, 00000001bjne Fhitjmp FnhitOPF0: ; BEQ Z set JMPtest ebx, 00000010bjne Fhitjmp FnhitOP30: ; BMI N set JMPtest ebx, 10000000bjne Fhitjmp FnhitOP70: ; BVS V set JMP test ebx, 01000000bjne Fhitjmp FnhitALIGNXMMFhit:add ebp, 3 ; hit 3 Cyclesmovsx ecx, byt[edx]lea esi, [ecx+esi+1]jmp PollInt ALIGNXMMFnhit:add ebp, 2 ; miss 2 Cyclesadd esi, 1jmp PollInt;***;ORA ; 09: #$2 cycles;05: ZERO PAGE3 cycles;15: ZERO PAGE X 4 cycles;0D: ABS 4 cycles;1D: ABS X 4 cycles (crossing page ++ cycles);19: ABS Y 4 cycles (crossing page ++ cycles);01: X INDIRECT 6 cycles;11: INDIRECT Y 4 cycles (crossing page ++ cycles);Algorithm:;; src |= AC;; SET_SIGN(src);; SET_ZERO(src);; AC = src;;*************************************************OP09: ; ORA #$ movzxeax,byt[edx] ;N - load #$ movzx ecx,byt[edi] ;N - load REG A orecx,eax ;U - ORA OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+2] ;U - 2 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP05: ; ORA ZERO PAGE movzxecx,byt[edx];N - load addr8Realmovzxeax,byt[ram+ecx];N - load VAL movzx ecx,byt[edi] ;N - load REG A orecx,eax ;U - ORA OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+3] ;U - 3 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP15: ; ORA ZERO PAGE X movzxecx,byt[edx];N - load addr8Realaddcl,byt[edi+4];U - ZERO PAGE X movdl,dl;V - movzxeax,byt[ram+ecx];N - load VAL movzx ecx,byt[edi] ;N - load REG A orecx,eax ;U - ORA OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+4] ;U - 4 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP0D: ; ORA ABS movzxecx,wot[edx];N - load addr16Realpushecx;U - leaebp,[ebp+4];V - 4 Cycles call nes_Read@4;N - movzx ecx,byt[edi] ;N - load REG A orcl,al ;U - ORA OPR andbl,07Dh;V - clr Z-N Flags mov$a,ecx;U - write Back REG A leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP1D: ; ORA ABS X movzxeax,wot[edx];N - load addr16Temp movzxedx,byt[edi+4];N - load REG X adddx,ax;U - ABS X addsi,2;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A orcl,al ;U - ORA OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP19: ; ORA ABS Y movzxeax,wot[edx];N - load addr16Temp movzxedx,byt[edi+8];N - load REG Yadddx,ax;U - ABS Yaddsi,2;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A orcl,al ;U - ORA OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP01: ; ORA X INDIRECT movzxeax,byt[edx];N - load addr8Real addal,byt[edi+4];U - X INDIRECT andbl,07Dh;V - clr Z-N Flags movdx,wot[ram+eax];U - load addr16Real addsi,1;V - ++ PC pushedx;U - leaebp,[ebp+6];V - 6 Cycles call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A orcl,al ;U - ORA OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP11: ; ORA INDIRECT Y movzxecx,byt[edx];N - load addr8Real movzxeax,wot[ram+ecx];N - load addr16Temp movzxedx,byt[edi+8];N - load REG Yadddx,ax;U - ABS Yaddsi,1;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A orcl,al ;U - ORA OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... ;***;EOR ; 49: #$2 cycles;45: ZERO PAGE3 cycles;55: ZERO PAGE X 4 cycles;4D: ABS 4 cycles;5D: ABS X 4 cycles (crossing page ++ cycles);59: ABS Y 4 cycles (crossing page ++ cycles);41: X INDIRECT 6 cycles;51: INDIRECT Y 4 cycles (crossing page ++ cycles);Algorithm:;; src ^= AC;; SET_SIGN(src);; SET_ZERO(src);; AC = src;;*************************************************OP49: ; EOR #$ movzxeax,byt[edx] ;N - load #$ movzx ecx,byt[edi] ;N - load REG A xorecx,eax ;U - EOR OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+2] ;U - 2 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP45: ; EOR ZERO PAGE movzxecx,byt[edx];N - load addr8Realmovzxeax,byt[ram+ecx];N - load VAL movzx ecx,byt[edi] ;N - load REG A xorecx,eax ;U - EOR OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+3] ;U - 3 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP55: ; EOR ZERO PAGE X movzxecx,byt[edx];N - load addr8Realaddcl,byt[edi+4];U - ZERO PAGE X movdl,dl;V - movzxeax,byt[ram+ecx];N - load VAL movzx ecx,byt[edi] ;N - load REG A xorecx,eax ;U - EOR OPRandebx,07Dh;V - clr Z-N Flags leaebp,[ebp+4] ;U - 4 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP4D: ; EOR ABS movzxecx,wot[edx];N - load addr16Realpushecx;U - leaebp,[ebp+4];V - 4 Cycles call nes_Read@4;N - movzx ecx,byt[edi] ;N - load REG A xorcl,al ;U - EOR OPRandbl,07Dh;V - clr Z-N Flags mov$a,ecx;U - write Back REG A leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP5D: ; EOR ABS X movzxeax,wot[edx];N - load addr16Temp movzxedx,byt[edi+4];N - load REG X adddx,ax;U - ABS X addsi,2;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A xorcl,al ;U - EOR OPRmovdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP59: ; EOR ABS Y movzxeax,wot[edx];N - load addr16Temp movzxedx,byt[edi+8];N - load REG Yadddx,ax;U - ABS Yaddsi,2;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A xorcl,al ;U - EOR OPRmovdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ...OP41: ; EOR X INDIRECT movzxeax,byt[edx];N - load addr8Real addal,byt[edi+4];U - X INDIRECT andbl,07Dh;V - clr Z-N Flags movdx,wot[ram+eax];U - load addr16Real addsi,1;V - ++ PC pushedx;U - leaebp,[ebp+6];V - 6 Cycles call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A xorcl,al ;U - EOR OPRmovdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP51: ; EOR INDIRECT Y movzxecx,byt[edx];N - load addr8Real movzxeax,wot[ram+ecx];N - load addr16Temp movzxedx,byt[edi+8];N - load REG Yadddx,ax;U - ABS Yaddsi,1;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A xorcl,al ;U - EOR OPRmovdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... ;***;AND ; 29: #$2 cycles;25: ZERO PAGE3 cycles;35: ZERO PAGE X 4 cycles;2D: ABS 4 cycles;3D: ABS X 4 cycles (crossing page ++ cycles);39: ABS Y 4 cycles (crossing page ++ cycles);21: X INDIRECT 6 cycles;31: INDIRECT Y 4 cycles (crossing page ++ cycles);Algorithm:;; src &= AC;; SET_SIGN(src);; SET_ZERO(src);; AC = src;;*************************************************OP29: ; AND #$ movzxeax,byt[edx] ;N - load #$ movzx ecx,byt[edi] ;N - load REG A andecx,eax ;U - AND OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+2] ;U - 2 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP25: ; AND ZERO PAGE movzxecx,byt[edx];N - load addr8Realmovzxeax,byt[ram+ecx];N - load VAL movzx ecx,byt[edi] ;N - load REG A andecx,eax ;U - AND OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+3] ;U - 3 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ...OP35: ; AND ZERO PAGE X movzxecx,byt[edx];N - load addr8Realaddcl,byt[edi+4];U - ZERO PAGE X movdl,dl;V - movzxeax,byt[ram+ecx];N - load VAL movzx ecx,byt[edi] ;N - load REG A andecx,eax ;U - AND OPR andebx,07Dh;V - clr Z-N Flags leaebp,[ebp+4] ;U - 4 Cycles orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags leaesi,[esi+1];U - ++ PC mov$a,ecx;V - write Back REG A jmpPollInt;N - ... OP2D: ; AND ABS movzxecx,wot[edx];N - load addr16Realpushecx;U - leaebp,[ebp+4];V - 4 Cycles call nes_Read@4;N - movzx ecx,byt[edi] ;N - load REG A andcl,al ;U - AND OPR andbl,07Dh;V - clr Z-N Flags mov$a,ecx;U - write Back REG A leaesi,[esi+2];V - ++ PC orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP3D: ; AND ABS X movzxeax,wot[edx];N - load addr16Temp movzxedx,byt[edi+4];N - load REG X adddx,ax;U - ABS X addsi,2;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A andcl,al ;U - AND OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP39: ; AND ABS Y movzxeax,wot[edx];N - load addr16Temp movzxedx,byt[edi+8];N - load REG Yadddx,ax;U - ABS Yaddsi,2;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A andcl,al ;U - AND OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP21: ; AND X INDIRECT movzxeax,byt[edx];N - load addr8Real addal,byt[edi+4];U - X INDIRECT andbl,07Dh;V - clr Z-N Flags movdx,wot[ram+eax];U - load addr16Real addsi,1;V - ++ PC pushedx;U - leaebp,[ebp+6];V - 6 Cycles call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A andcl,al ;U - AND OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... OP31: ; AND INDIRECT Y movzxecx,byt[edx];N - load addr8Real movzxeax,wot[ram+ecx];N - load addr16Temp movzxedx,byt[edi+8];N - load REG Yadddx,ax;U - ABS Yaddsi,1;V - ++ PC pushedx;U - PUSH arg wait call PROC leaebp,[ebp+4];V - 4 Cycles andbl,07Dh;U - clr Z-N Flags subah,dh;V - test CrossPage adcebp,0;U - moveax,eax;V - call nes_Read@4;N - call PROC movzx ecx,byt[edi] ;N - load REG A andcl,al ;U - AND OPR movdl,dl;V - mov$a,ecx;U - write Back REG A moveax,eax;V - orebx,dwot[zn_Table+ecx*4];V - reset Z-N Flags jmpPollInt;V - /N ... ;***;JMP ;4C: ABS 3 cycles ;6C: inDirect5 cycles;Algorithm:;;PC = (src);;;*************************************************OP4C: ; JMP ABS mov si, wot[edx];U - get PC addbp,3;V - 3 Cycles jmp PollInt ;N - OP6C: ; in-direct JMP expection crossing page boundaries in 6C ; NES JMP(only 6C)'s BUG: if addr is 0x--FF(Crossing Page) IP's High Bit Will Not Add ; ; $2500: 33; $25FF: 76; $2600: 89; $7574: 6C FF 25; PC <- $7574 ;; Step1-> Get PC's Low Bit FF ; Step2-> Get PC's High Bit 25 ; $(25FF-2600) will crossing page so low bit is $25FF high Bit is $2500; jmp to $3376 ... movzx eax, wot[edx] ;N - load indirect addr ...push eax ;U - push arg wait call nes_Read@4/nes_Readw@4addebp, 5 ;V - 5 Cyclescmp al, 0FFh ;U - low addr is FF ? jne noCrossPageBUG;V - FF:no jmp else immed read word no CrossPage mov $t1, eax ;U - save addr movebp,ebp;V - call nes_Read@4 ;N - call read PROC - BYTEmov esi,eax ;U - addr - low bit mov eax, $t1 ;V - load org addr sub eax, 0FFh ;U - crossPage BUG deal andesi,0FFh;V - limit byte push eax ;U - push arg wait call nes_Read@4moveax,eax;V - call nes_Read@4;N - call read PROC - BYTEshleax, 8;U - shift to high 8 bits movecx,ecx;V - oresi,eax;U - get PC over jmp PollInt ;V - /N ALIGNXMM noCrossPageBUG:call nes_Readw@4;- N call read PROC - WORDmov esi, eax ;- U PC <- EAX jmp PollInt ; - V/N ;***;JSR20:ABS 6 cycles ;;;Algorithm:;;PC--;;PUSH((PC >> 8) & 0xff);/* Push return address onto the stack. */;PUSH(PC & 0xff);;PC = (src);;;*************************************************OP20: ; JSR movzxeax,wot[edx];N - load future PC mov ecx, $s ;U - load REG S addebp,6;V - 6 Cycles andecx,0FFh;U - limits bits leaedx,[esi+1];V - ++ PC movesi,eax;U - write back PC moveax,eax;V - mov wot[ram+0100h+ecx-1], dx ;U - wrte back STACK PC subcx,2;V - /N STACK --mov$s,ecx;U - write back STACKjmp PollInt ;V - /N continue deal interrupt ;***;RTI40 ;;;Algorithm:;;src = PULL();; SET_SR(src);; src = PULL();; src |= (PULL() << 8);/* Load return address from stack. */; PC = (src);;;*************************************************OP40: ; RTImovecx,$s;U - load REG S addebp,6;V - 6 Cycles andecx,0FFh;U - moveax,eax;V - leaecx,[ecx+3] ;U - ++ STACK movebx,ebx;V - mov bl, byt[ram+0100h+ecx-2];U - write back REG P moval,al;V - mov si, wot[ram+0100h+ecx-1];U - write back REG PC movbx,bx;V - mov$s,ecx;U - write back REG Sjmp PollInt ;V - /N continue deal interrupt ;***;RTS60 ;;;Algorithm:;;src = PULL();; src += ((PULL()) << 8) + 1;/* Load return address from stack and add 1. */; PC = (src);;;*************************************************OP60: ; RTS mov ecx, $s ;U - load REG S addebp, 6 ;V - 6 Cycles and ecx, 255 ;U - limit Bitsmoveax,eax;V - add ecx, 2 ;U - ++STACK moveax,eax;V - mov si, wot[ram+0100h+ecx-1] ;U - load PC movax,ax;V - mov $s, ecx ;U - write back S leaesi, [esi+1];V - ++ PC jmp PollInt ;V - /N continue deal interrupt OP18: ; CLC addebp,2 andebx,11111110bjmp PollInt OPD8: ; CLD addebp,2 andebx,11110111bjmp PollInt OP58: ; CLI addebp,2 andebx,11111011bjmp PollInt OPB8: ; CLV addebp,2 andebx,10111111bjmp PollInt OP38: ; SEC addebp,2 orebx,00000001bjmp PollInt OPF8: ; SED addebp,2 orebx,00001000bjmp PollInt OP78: ; SEI addebp,2 orebx,00000100bjmp PollInt ;***;LDA ;A9: ACC2 cycles ;A5: ZERO PAGE3 cycles;B5: ZERO PAGE X 4 cycles;AD: ABS 4 cycles;BD: ABS X 4 cycles (test cross page);B9: ABS Y 4 cycles (test cross page);A1: X INDIRECT 6 cycles;B1: INDIRECT Y 5 cycles (test cross page);XA5: X REG2 cycles ;XA6: ZERO PAGE3 cycles;X B6: ZERO PAGE Y 4 cycles ;X AE: ABS4 cycles ;XBE: ABS Y4 cycles (test cross page);YA0: Y REG2 cycles ;YA4: ZERO PAGE3 cycles;Y B4: ZERO PAGE X 4 cycles ;Y AC: ABS4 cycles ;YBC: ABS X4 cycles (test cross page);;Algorithm:;; SET_SIGN(src);; SET_ZERO(src);; AC = (src);;;*************************************************; =====;A; =====OPA9: ; LDA #$movzxeax,byt[edx];N - eax <- #$ mov$a,eax;U - A <- eax andebx,07Dh;V - clr Z-N leaebp,[ebp+2];U - 2 Cycles leaesi,[esi+1];V - ++ PC orebx,dwot[zn_Table+eax*4];U - set Z-N jmpPollInt;V - OPA5: ; LDA ZERO PAGE movzx eax, byt[edx];N - eax <- a8Real moval,byt[ram+eax];U - eax <- MEM andbl,07Dh;V - clr Z-N mov$a,eax;U - A <- MEM leaebp,[ebp+3];V - 3 Cycles leaesi,[esi+1];U - ++ PC orebx,dwot[zn_Table+eax*4];V - set Z-N jmp PollInt ;N - OPB5: ; LDA ZERO PAGE Xmovzx eax, byt[edx];N - eax <- a8Temp addal, byt[edi+4];U - eax <- a8Real movdl, dl ;V - moval,byt[ram+eax];U - eax <- MEM andbl,07Dh;V - clr Z-N mov$a,eax;U - A <- MEM leaebp,[ebp+4];V - 4 Cycles leaesi,[esi+1];U - ++ PC orebx,dwot[zn_Table+eax*4];V - set Z-N jmp PollInt ;N - OPAD: ; LDA ABS --movzx eax, wot[edx];N - eax <- a16Real pusheax;U - leaebp,[ebp+4];V - 4 Cycles call nes_Read@4;N - andeax,0FFh;U - movedx,edx;V - andebx,07Dh;U - clr Z-N mov$a,eax;V - A <- MEM orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+2];V - ++ PC jmp PollInt ;N - OPBD: ; LDA ABS X movzx eax, wot[edx];N - eax <- a16Temp movzx ecx, byt[edi+4];N - ecx <- X add ecx,eax ;U - leaesi,[esi+2];V - ++ PC push ecx ;U - moveax,eax ;V - andbl,07Dh;U - clr Z-N sub ah, ch ;V - test CrossPage adc ebp, 4 ;U - mov ebx, ebx ;V - call nes_Read@4;N - mov$a,eax;U - A <- MEM andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmp PollInt ;V/N - OPB9: ; LDA ABS Y movzx eax, wot[edx];N - eax <- a16Temp movzx ecx, byt[edi+8];N - ecx <- Y add ecx,eax ;U - leaesi,[esi+2];V - ++ PC push ecx ;U - moveax,eax ;V - andbl,07Dh;U - clr Z-N sub ah, ch ;V - test CrossPage adc ebp, 4 ;U - mov ebx, ebx ;V - call nes_Read@4;N - mov$a,eax;U - A <- MEM andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmp PollInt ;V/N - OPA1: ; LDA X INDIRECT movzxeax,byt[edx];N - eax <- a8Temp addal,byt[edi+4];U - eax <- a8Real andbl,07Dh;V - clr Z-N movcx,wot[ram+eax];U - ecx <- a16Real addbp,6;V - 6 Cycles pushecx;U - leaesi,[esi+1];V - ++ PC call nes_Read@4;N - mov$a,eax;U - A <- MEM andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmp PollInt ;V - /N ... OPB1: ; LDA INDIRECT Ymovzx eax, byt[edx];N - eax <- a8Real movzx eax, wot[ram+eax];N - eax <- a16Tempmovzx ecx, byt[edi+8];N - ecx <- Y add ecx,eax ;U - leaesi,[esi+1];V - ++ PC push ecx ;U - moveax,eax ;V - andbl,07Dh;U - clr Z-N sub ah, ch ;V - test CrossPage adc ebp, 5 ;U - mov ebx, ebx ;V - call nes_Read@4;N - mov$a,eax;U - A <- MEM andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmp PollInt ;V/N - ; =====;X; =====OPA2: ; LDX #$movzxeax,byt[edx];N - eax <- #$ mov$x,eax;U - X <- eax andebx,07Dh;V - clr Z-N leaebp,[ebp+2];U - 2 Cycles leaesi,[esi+1];V - ++ PC orebx,dwot[zn_Table+eax*4];U - set Z-N jmpPollInt;V - OPA6: ; LDX ZERO PAGE movzx eax, byt[edx];N - eax <- a8Real moval,byt[ram+eax];U - eax <- MEM andbl,07Dh;V - clr Z-N mov$x,eax;U - X <- MEM leaebp,[ebp+3];V - 3 Cycles leaesi,[esi+1];U - ++ PC orebx,dwot[zn_Table+eax*4];V - set Z-N jmp PollInt ;N - OPB6: ; LDX ZERO PAGE Y movzx eax, byt[edx];N - eax <- a8Temp addal, byt[edi+8];U - eax <- a8Real movdl, dl ;V - moval,byt[ram+eax];U - eax <- MEM andbl,07Dh;V - clr Z-N mov$x,eax;U - X <- MEM leaebp,[ebp+4];V - 4 Cycles leaesi,[esi+1];U - ++ PC orebx,dwot[zn_Table+eax*4];V - set Z-N jmp PollInt ;N - OPAE: ; LDX ABS movzx eax, wot[edx];N - eax <- a16Real pusheax;U - leaebp,[ebp+4];V - 4 Cycles call nes_Read@4;N - andeax,0FFh;U - movedx,edx;V - andebx,07Dh;U - clr Z-N mov$x,eax;V - X <- MEM orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+2];V - ++ PC jmp PollInt ;N - OPBE: ; LDX ABS Y movzx eax, wot[edx];N - eax <- a16Temp movzx ecx, byt[edi+8];N - ecx <- Y add ecx,eax ;U - leaesi,[esi+2];V - ++ PC push ecx ;U - moveax,eax ;V - andbl,07Dh;U - clr Z-N sub ah, ch ;V - test CrossPage adc ebp, 4 ;U - mov ebx, ebx ;V - call nes_Read@4;N - mov$x,eax;U - X <- MEM andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmp PollInt ;V/N - ; =====;y; =====OPA0: ; LDY #$movzxeax,byt[edx];N - eax <- #$ mov$y,eax;U - Y <- eax andebx,07Dh;V - clr Z-N leaebp,[ebp+2];U - 2 Cycles leaesi,[esi+1];V - ++ PC orebx,dwot[zn_Table+eax*4];U - set Z-N jmpPollInt;V - OPA4: ; LDY ZERO PAGE movzx eax, byt[edx];N - eax <- a8Real moval,byt[ram+eax];U - eax <- MEM andbl,07Dh;V - clr Z-N mov$y,eax;U - Y <- MEM leaebp,[ebp+3];V - 3 Cycles leaesi,[esi+1];U - ++ PC orebx,dwot[zn_Table+eax*4];V - set Z-N jmp PollInt ;N - OPB4: ; LDY ZERO PAGE X movzx eax, byt[edx];N - eax <- a8Temp addal, byt[edi+4];U - eax <- a8Real movdl, dl ;V - moval,byt[ram+eax];U - eax <- MEM andbl,07Dh;V - clr Z-N mov$y,eax;U - Y <- MEM leaebp,[ebp+4];V - 4 Cycles leaesi,[esi+1];U - ++ PC orebx,dwot[zn_Table+eax*4];V - set Z-N jmp PollInt ;N - OPAC: ; LDY ABSmovzx eax, wot[edx];N - eax <- a16Real pusheax;U - leaebp,[ebp+4];V - 4 Cycles call nes_Read@4;N - andeax,0FFh;U - movedx,edx;V - andebx,07Dh;U - clr Z-N mov$y,eax;V - Y <- MEM orebx,dwot[zn_Table+eax*4] ;U - set Z-N leaesi,[esi+2];V - ++ PC jmp PollInt ;N - OPBC: ; LDY ABS X movzx eax, wot[edx];N - eax <- a16Temp movzx ecx, byt[edi+4];N - ecx <- X add ecx,eax ;U - leaesi,[esi+2];V - ++ PC push ecx ;U - moveax,eax ;V - andbl,07Dh;U - clr Z-N sub ah, ch ;V - test CrossPage adc ebp, 4 ;U - mov ebx, ebx ;V - call nes_Read@4;N - mov$y,eax;U - Y <- MEM andeax,0FFh;V - orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmp PollInt ;V/N - ; trans REG to REG ; tXN;X source REG; N target REG ; TXS not set Z-N flag (only this.. other must set Z-N flag)... ; cycles all 2 cycles ... OPAA: ; TAXand ebx, 07Dh ;U - mov eax, $a ;V - eax <- A mov $x, eax ;U - X <- eax and eax, 0FFh ;V - add ebp, 2 ;U - orebx, dwot[zn_Table+eax*4];V - jmp PollInt;N - OP8A: ; TXAand ebx, 07Dh ;U - mov eax, $x ;V - eax <- Xmov $a, eax ;U - A <- eax and eax, 0FFh ;V - add ebp, 2 ;U - orebx, dwot[zn_Table+eax*4];V - jmp PollInt;N - OPA8: ; TAYand ebx, 07Dh ;U - mov eax, $a ;V - eax <- A mov $y, eax ;U - Y <- eax and eax, 0FFh ;V - add ebp, 2 ;U - orebx, dwot[zn_Table+eax*4];V - jmp PollInt;N - OP98: ; TYAand ebx, 07Dh ;U - mov eax, $y ;V - eax <- Y mov $a, eax ;U - A <- eax and eax, 0FFh ;V - add ebp, 2 ;U - orebx, dwot[zn_Table+eax*4];V - jmp PollInt;N - OPBA: ; TSXand ebx, 07Dh ;U - mov eax, $s ;V - eax <- Smov $x, eax ;U - X <- eax and eax, 0FFh ;V - add ebp, 2 ;U - orebx, dwot[zn_Table+eax*4];V - jmp PollInt;N - OP9A: ; TXS (RTOR only this not set flag)mov eax, $x ;U - eax <- Xadd ebp, 2 ;V - mov $s, eax ;U - S <- eax jmp PollInt;N - ;***;ASL ; 0A: ACC2 cycles;06: ZERO PAGE5 cycles;16: ZERO PAGE X 6 cycles;0E: ABS 6 cycles;1E: ABS X 7 cycles ;Algorithm:;; SET_CARRY(src & 0x80);; src <<= 1;; src &= 0xff;; SET_SIGN(src);; SET_ZERO(src);; STORE src in memory or accumulator depending on addressing mode.;;************************************************* OP0A: ; ASL A - 2 cyclesmovzxeax,byt[edi];N - eax <- A andebx,01111100b;U - clr N-Z-C leaebp,[ebp+2];V - 2 Cycles shlal,1;U - ASL A movdl,dl;V - adcebx,0;U - set C mov$a,eax;V - A <- eax orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmpPollInt;V - /N OP06: ; ASL ZERO PAGE 5 cycles movzxedx,byt[edx];N - edx <- a8Realmovzxeax,byt[ram+edx];N - eax <- MEM andebx,01111100b;U - clr N-Z-Cleaebp,[ebp+5];V - 5 Cycles shlal,1;U - ASL movdl,dl;V - adcebx,0;U - set C leaesi,[esi+1];V - ++ PC movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmpPollInt;N - OP16: ; ASL ZERO PAGE X movzxedx,byt[edx];N - edx <- a8Tempadddl,byt[edi+4];U - edx <- a8Real moval,al;V - movzxeax,byt[ram+edx];N - eax <- MEM andebx,01111100b;U - clr N-Z-C leaebp,[ebp+6];V - 6 Cycles shlal,1;U - ASL movdl,dl;V - adcebx,0;U - set C leaesi,[esi+1];V - ++ PC movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmpPollInt;N - OP0E: ; ASL ABS movax,wot[edx];U - eax <- a16Realaddsi,2;V - ++ PC mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purifyandebx,01111100b;V - clr Z-N-C shlal,1;U - ASL movdl,dl;V - adcebx,0;U - set C leaebp,[ebp+6];V - 6 Cycles orebx,dwot[zn_Table+eax*4];U - set Z-N pusheax;V - push MEM push$t1;U - push a16Realmoveax,eax;V - call nes_Write@8;N - jmp PollInt;N - OP1E: ; ASL ABS X movzxecx,byt[edi+4];N - ecx <- X movax,wot[edx];U - eax <- a16Temp movbx,bx;V - addax,cx;U - eax <- a16Realaddsi,2;V - ++ PC mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purify andebx,01111100b;V - clr Z-N-C shlal,1;U - ASL movdl,dl;V - adcebx,0;U - set C leaebp,[ebp+7];V - 7 Cycles orebx,dwot[zn_Table+eax*4];U - set Z-N pusheax;V - push MEM push$t1;U - push a16Realmoveax,eax;V - call nes_Write@8;N - jmp PollInt;N - ;***;LSR ; 4A: ACC2 cycles;46: ZERO PAGE5 cycles;56: ZERO PAGE X 6 cycles;4E: ABS 6 cycles;5E: ABS X 7 cycles ;Algorithm:;; SET_CARRY(src & 0x01);; src >>= 1;; SET_SIGN(src);; SET_ZERO(src);; STORE src in memory or accumulator depending on addressing mode.;;*************************************************OP4A: ; LSR A movzxeax,byt[edi];N - eax <- A andebx,01111100b;U - clr N-Z-C leaebp,[ebp+2];V - 2 Cycles shral,1;U - LSR A movdl,dl;V - adcebx,0;U - set C mov$a,eax;V - A <- eax orebx,dwot[zn_Table+eax*4] ;U - set Z-N jmpPollInt;V - /N OP46: ; LSR ZERO PAGE movzxedx,byt[edx];N - edx <- a8Realmovzxeax,byt[ram+edx];N - eax <- MEM andebx,01111100b;U - clr N-Z-Cleaebp,[ebp+5];V - 5 Cycles shral,1;U - LSR movdl,dl;V - adcebx,0;U - set C leaesi,[esi+1];V - ++ PC movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmpPollInt;N - OP56: ; LSR ZERO PAGE X movzxedx,byt[edx];N - edx <- a8Tempadddl,byt[edi+4];U - edx <- a8Real moval,al;V - movzxeax,byt[ram+edx];N - eax <- MEM andebx,01111100b;U - clr N-Z-C leaebp,[ebp+6];V - 6 Cycles shral,1;U - LSR movdl,dl;V - adcebx,0;U - set C leaesi,[esi+1];V - ++ PC movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmpPollInt;N - OP4E: ; LSR ABS movax,wot[edx];U - eax <- a16Realaddsi,2;V - ++ PC mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purifyandebx,01111100b;V - clr Z-N-C shral,1;U - LSR movdl,dl;V - adcebx,0;U - set C leaebp,[ebp+6];V - 6 Cycles orebx,dwot[zn_Table+eax*4];U - set Z-N pusheax;V - push MEM push$t1;U - push a16Realmoveax,eax;V - call nes_Write@8;N - jmp PollInt;N - OP5E: ; LSR ABS X movzxecx,byt[edi+4];N - ecx <- X movax,wot[edx];U - eax <- a16Temp movbx,bx;V - addax,cx;U - eax <- a16Realaddsi,2;V - ++ PC mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purify andebx,01111100b;V - clr Z-N-C shral,1;U - LSR movdl,dl;V - adcebx,0;U - set C leaebp,[ebp+7];V - 7 Cycles orebx,dwot[zn_Table+eax*4];U - set Z-N pusheax;V - push MEM push$t1;U - push a16Realmoveax,eax;V - call nes_Write@8;N - jmp PollInt;N - ;***;ROL ; 2A: ACC2 cycles;26: ZERO PAGE5 cycles;36: ZERO PAGE X 6 cycles;2E: ABS 6 cycles;3E: ABS X 7 cycles ;Algorithm:;; src <<= 1;; if (IF_CARRY()) {;src |= 0x1;;}; SET_CARRY(src > 0xff);; src &= 0xff;; SET_SIGN(src);; SET_ZERO(src);; STORE src in memory or accumulator depending on addressing mode.;;*************************************************OP2A: ; ROL A movzxeax,byt[edi] ;N - eax <- A and ebx, 01111101b ;U - set C leaebp,[ebp+2] ;V - 2 Cycles shrebx,1;U - throw C moveax,eax;V - rclal,1 ;N - ROL A rclbl,1;N - receive C mov$a,eax;U - A <- eax orebx,dwot[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP26: ; ROL ZERO PAGE movzxedx,byt[edx] ;N - edx <- a8Realmovzxeax,byt[ram+edx];N - eax <- MEM and ebx, 01111101b ;U - set C leaebp,[ebp+5] ;V - 5 Cycles shrebx,1;U - throw C leaesi,[esi+1];V - ++ PC rclal,1 ;N - ROL rclbl,1;N - receive C movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP36: ; ROL ZERO PAGE X movzxedx,byt[edx] ;N - edx <- a8Temp adddl,byt[edi+4];U - edx <- a8Real movbl,bl ;V - movzxeax,byt[ram+edx];N - eax <- MEM and ebx, 01111101b ;U - set C leaebp,[ebp+6] ;V - 6 Cycles shrebx,1;U - throw C leaesi,[esi+1];V - ++ PC rclal,1 ;N - ROL rclbl,1;N - receive C movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP2E: ; ROL ABS movax,wot[edx];U - eax <- a16Real addsi,2 ;V - ++ PC mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purify andebx,01111101b ;V - clr Z-N-Cshrebx,1 ;U - throw C leaebp,[ebp+6] ;V - 6 Cycles rclal,1 ;N - ROL rclbl,1;N - receive C pusheax;U - push$t1;V - movedx,edx;U - orebx,dwot[zn_Table+eax*4] ;V - reset Z-N Flags callnes_Write@8;N - jmp PollInt ;N - OP3E: ; ROL ABS X movzx ecx, byt[edi+4];N - ecx <- X movax,wot[edx];U - eax <- a16Temp addsi,2 ;V - ++ PC addax,cx;U - eax <- a16Realmovdx,dx ;V - mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purify andebx,01111101b ;V - clr Z-N-Cshrebx,1 ;U - throw C leaebp,[ebp+7] ;V - 7 Cycles rclal,1 ;N - ROL rclbl,1;N - receive C pusheax;U - push$t1;V - movedx,edx;U - orebx,dwot[zn_Table+eax*4] ;V - reset Z-N Flags callnes_Write@8;N - jmp PollInt ;N - ;***;ROR ; 6A: ACC2 cycles;66: ZERO PAGE5 cycles;76: ZERO PAGE X 6 cycles;6E: ABS 6 cycles;7E: ABS X 7 cycles ;Algorithm:;; if (IF_CARRY()) {;src |= 0x100;;}; SET_CARRY(src & 0x01);; src >>= 1;; SET_SIGN(src);; SET_ZERO(src);; STORE src in memory or accumulator depending on addressing mode.;;*************************************************OP6A: ; ROR A movzxeax,byt[edi] ;N - eax <- A and ebx, 01111101b ;U - set C leaebp,[ebp+2] ;V - 2 Cycles shrebx,1;U - throw C moveax,eax;V - rcral,1 ;N - ROR A rclbl,1;N - receive C mov$a,eax;U - A <- eax orebx,dwot[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP66: ; ROR ZERO PAGE movzxedx,byt[edx] ;N - edx <- a8Realmovzxeax,byt[ram+edx];N - eax <- MEM and ebx, 01111101b ;U - set C leaebp,[ebp+5] ;V - 5 Cycles shrebx,1;U - throw C leaesi,[esi+1];V - ++ PC rcral,1 ;N - ROR rclbl,1;N - receive C movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP76: ; ROR ZERO PAGE X movzxedx,byt[edx] ;N - edx <- a8Temp adddl,byt[edi+4];U - edx <- a8Real movbl,bl ;V - movzxeax,byt[ram+edx];N - eax <- MEM and ebx, 01111101b ;U - set C leaebp,[ebp+6] ;V - 6 Cycles shrebx,1;U - throw C leaesi,[esi+1];V - ++ PC rcral,1 ;N - RORrclbl,1;N - receive C movbyt[ram+edx], al;U - MEM <- eax orbl,byt[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP6E: ; ROR ABS movax,wot[edx];U - eax <- a16Real addsi,2 ;V - ++ PC mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purify andebx,01111101b ;V - clr Z-N-Cshrebx,1 ;U - throw C leaebp,[ebp+6] ;V - 6 Cycles rcral,1 ;N - RORrclbl,1;N - receive C pusheax;U - push$t1;V - movedx,edx;U - orebx,dwot[zn_Table+eax*4] ;V - reset Z-N Flags callnes_Write@8;N - jmp PollInt ;N - OP7E: ; ROR ABS X movzx ecx, byt[edi+4];N - ecx <- X movax,wot[edx];U - eax <- a16Temp addsi,2 ;V - ++ PC addsi,2 ;V - ++ PC addax,cx;U - eax <- a16Realmovdx,dx ;V - mov$t1,eax;U - t1 <- a16Realpusheax;V - callnes_Read@4;N - andeax,0FFh;U - purify andebx,01111101b ;V - clr Z-N-Cshrebx,1 ;U - throw C leaebp,[ebp+7] ;V - 7 Cycles rcral,1 ;N - RORrclbl,1;N - receive C pusheax;U - push$t1;V - movedx,edx;U - orebx,dwot[zn_Table+eax*4] ;V - reset Z-N Flags callnes_Write@8;N - jmp PollInt ;N - OP48: ; PHA moveax, $a ;U - eax <- A movedx,$s;V - edx <- S andedx,0FFh;U - purify addebp,3;V - 3 Cyclesmov byt[ram+0100h+edx], al ;U - STACK <- A decdl ;V - STACK -- mov$s,edx;U - jmpPollInt;V -OP08: ; PHP movedx,$s;U - edx <- S addebp,3;V - 3 Cyclesandedx,0FFh;U - purify orebx,B_FLAG;V - set B Flagmov byt[ram+0100h+edx], bl ;U - STACK <- Pdecdl ;V - STACK -- mov$s,edx;U - jmpPollInt;V - OP68: ; PLA mov edx, $s ;U - edx <- S andebx,07Dh;V - clr Z-N andedx,0FFh;U - purify addebp,4;V - 4 Cyclesmoval,byt[ram+0101h+edx] ;U - A <- STACK adddl,1;V - ++ STACK andeax,0FFh;U - purify mov$s,edx;V - mov $a, eax ;U - orebx,dwot[zn_Table+eax*4] ;V - set Z-N jmp PollInt ;N - OP28: ; PLP mov edx, $s ;U - edx <- S addebp,4;V - 4 Cyclesandedx,0FFh;U - purify movecx,ecx;V - movbl,byt[ram+0101h+edx] ;U - P <- STACK adddl,1;V - ++ STACK mov$s,edx;U - jmp PollInt ;V - ;***;BIT ;24: ZERO PAGE3 cycles;2C: ABS 4 cycles;Algorithm:;; SET_SIGN(src);; SET_OVERFLOW(0x40 & src);; SET_ZERO(src & AC);;*************************************************OP24: ; BIT ZERO PAGE 3 cyclesmovzx eax,byt[edx];N - eax <- a8Real moval,byt[ram+eax];U - eax <- MEM andbl,00111101b;V - clr N-Z-V movecx,$a;U - ecx <- A leaesi,[esi+1] ;V - ++ PC test al, cl ;U - movbl, bl ;V - setz cl ;N - set Z andeax,0C0h ;U - get N-V andecx,001h ;V - get Z leaedx, [eax+ecx*2] ;U - mix N-V-Z leaebp, [ebp+3] ;V - 3 Cycles orebx, edx ;U - set N-V-Z jmpPollInt;V - OP2C: ; BIT ABS 4 cycles movax,wot[edx];U - eax <- a16Realandbx,00111101b;V - clr N-Z-Vpusheax;U - leaesi,[esi+2] ;V - ++ PC callnes_Read@4 ;N - movecx,$a;U - ecx <- A leaebx,[ebx];V - test al, cl ;U - movbl, bl ;V - setz cl ;N - set Z andeax,0C0h ;U - get N-V andecx,001h ;V - get Z leaedx, [eax+ecx*2] ;U - mix N-V-Z leaebp, [ebp+4] ;V - 4 Cycles orebx, edx ;U - set N-V-Z jmpPollInt;V - ;***;STA ;85: ZERO PAGE3 cycles;95: ZERO PAGE X 4 cycles;80: ABS 4 cycles;90: ABS X 5 cycles ;99: ABS Y 5 cycles;81: X INDIRECT 6 cycles;91: INDIRECT Y 6 cycles (no test cross page);X86: ZERO PAGE3 cycles;X 96: ZERO PAGE Y 4 cycles ;X 8E: ABS4 cycles ;Y84:ZERO PAGE3 cycles;Y94: ZERO PAGE X4 cycles;Y8C: ABS4 cycles;;Algorithm:;; STORE(address, A);;;*************************************************; =====;A; =====OP85: ; STA ZERO PAGE movzx eax, byt[edx];N - eax <- a8Real movecx,$a;U - ecx <- A leaebp,[ebp+3];V - 3 Cycles movbyt[ram+eax], cl;U - MEM <- ecx movbl,bl;V - leaesi,[esi+1];U - ++ PC jmpPollInt;V - OP95: ; STA ZERO PAGE X movzx eax, byt[edx];N - eax <- a8Temp addal, byt[edi+4];U - movdl, dl;V -movecx,$a;U - ecx <- Aleaebp,[ebp+4];V - 4 Cycles movbyt[ram+eax], cl;U - MEM <- ecx movbl,bl;V - leaesi,[esi+1];U - ++ PC jmpPollInt;V - OP8D: ; STA ABS movzx eax, wot[edx];N - eax <- a16Real push$a;U - pusheax;V - callnes_Write@8;N - leaesi,[esi+2];U - ++ PC leaebp,[ebp+4];V - 4 Cycles jmp PollInt ;V - OP9D: ; STA ABS X movzx eax, wot[edx];N - eax <- a16Temp movzxecx,byt[edi+4];N - ecx <- X push$a;U - addeax,ecx;V - eax <- a16Realpusheax;U - leaebp,[ebp+5];V - 5 Cycles callnes_Write@8;N - leaesi,[esi+2];U - ++ PC jmp PollInt ;V - /N ... OP99: ; STA ABS Y movzx eax, wot[edx];N - eax <- a16Temp movzxecx,byt[edi+8];N - ecx <- Ypush$a;U - addeax,ecx;V - eax <- a16Realpusheax;U - leaebp,[ebp+5];V - 5 Cycles callnes_Write@8;N - leaesi,[esi+2];U - ++ PC jmp PollInt ;V - /N ... OP81: ; STA X INDIRECT movzxeax,byt[edx];N - eax <- a8Tempaddal,byt[edi+4];U - eax <- a8Realmovcl,cl;V - movdx,wot[eax+ram];U - edx <- a16Real addbp,6;V - 6 Cycles push$a;U - pushedx;V - call nes_Write@8;N - call nes_Write@8 addesi,1;U - ++ PC jmpPollInt;V - OP91: ; STA INDIRECT Ymovzxeax,byt[edx];N - eax <- a8Realmovzxedx,byt[edi+8];N - edx <- Ymovcx,wot[ram+eax];U - ecx <- a16Tempaddsi,1;V - ++ PC addcx,dx;U - ecx <- a16Realaddbp,6;V - 6 Cycles push$a;U - pushecx;V - call nes_Write@8;N - jmpPollInt;V - ; =====;X; =====OP86: ; STX ZERO PAGE movzx eax, byt[edx];N - eax <- a8Real movecx,$x;U - ecx <- X leaebp,[ebp+3];V - 3 Cycles movbyt[ram+eax], cl;U - MEM <- ecx movbl,bl;V - leaesi,[esi+1];U - ++ PC jmpPollInt;V - OP96: ; STX ZERO PAGE Y movzx eax, byt[edx];N - eax <- a8Temp addal, byt[edi+8];U - movdl, dl;V -movecx,$x;U - ecx <- X leaebp,[ebp+4];V - 4 Cycles movbyt[ram+eax], cl;U - MEM <- ecx movbl,bl;V - leaesi,[esi+1];U - ++ PC jmpPollInt;V - OP8E: ; STX ABS movzx eax, wot[edx];N - eax <- a16Real push$x;U - pusheax;V - callnes_Write@8;N - leaesi,[esi+2];U - ++ PC leaebp,[ebp+4];V - 4 Cycles jmp PollInt ;V - ; =====;y; =====OP84: ; STY ZERO PAGE movzx eax, byt[edx];N - eax <- a8Real movecx,$y;U - ecx <- Y leaebp,[ebp+3];V - 3 Cycles movbyt[ram+eax], cl;U - MEM <- ecx movbl,bl;V - leaesi,[esi+1];U - ++ PC jmpPollInt;V - OP94: ; STY ZERO PAGE Xmovzx eax, byt[edx];N - eax <- a8Temp addal, byt[edi+4];U - movdl, dl;V -movecx,$y;U - ecx <- Y leaebp,[ebp+4];V - 4 Cycles movbyt[ram+eax], cl;U - MEM <- ecx movbl,bl;V - leaesi,[esi+1];U - ++ PC jmpPollInt;V - OP8C: ; STY ABS movzx eax, wot[edx];N - eax <- a16Real push$y;U - pusheax;V - callnes_Write@8;N - leaesi,[esi+2];U - ++ PC leaebp,[ebp+4];V - 4 Cycles jmp PollInt ;V - OP00: OPEA:; When the MOS 6502 processor was modified into the Ricoh 2A03 chip for the NES,\; the BRK (Force Break) opcode was eliminated. ; Thus, the BRK command doesn't actually do anything on the NES and is effectively identical to NOP. ; Because of this, when you see a BRK in decompiled NES code,\; you can be fairly certain that the #00 value is either game data or unused.; Having a BRK execute on the NES won't harm anything, it will only eat up a clock cycle to process. ; You can take advantage of this feature when making game cheats. ; For example, if you want to change an opcode that takes a two-byte operand into an opcode that uses a one-byte operand,\ ; you can ignore the second byte of the operand if it is a #00 because the NES will simply treat it as a BRK, which is ignored.; On an original MOS 6502 processor,\; BRK would set the Interrupt Flag to prevent further interrupts and then move the Program Counter Register to the new location.; Addressing Modes; ==================================================================; Addressing ModeAssembly Language FormOpcode# Bytes# Cycles; =========================================== ====== =====; Implied BRK 00 12; ========================================================================; ref link: www.thealmightyguru.com/Games/Hacking/Wiki/index.php?title=BRK; ========================================================================add ebp,2 jmp PollInt OP02:OP03:OP04:OP07:OP0B:OP0C:OP0F:OP12:OP13:OP14:OP17:OP1A:OP1B:OP1C:OP1F:OP22:OP23:OP27:OP2B:OP2F:OP32:OP33:OP34:OP37:OP3A:OP3B:OP3C:OP3F:OP42:OP43:OP44:OP47:OP4B:OP4F:OP52:OP53:OP54:OP57:OP5A:OP5B:OP5C:OP5F:OP62:OP63:OP64:OP67:OP6B:OP6F:OP72:OP73:OP74:OP77:OP7A:OP7B:OP7C:OP7F:OP80:OP82:OP83:OP87:OP89:OP8B:OP8F:OP92:OP93:OP97:OP9B:OP9C:OP9E:OP9F:OPA3:OPA7:OPAB:OPAF:OPB2:OPB3:OPB7:OPBB:OPBF:OPC2:OPC3:OPC7:OPCB:OPCF:OPD2:OPD3:OPD4:OPD7:OPDA:OPDB:OPDC:OPDF:OPE2:OPE3:OPE7:OPEB:OPEF:OPF2:OPF3:OPF4:OPF7:OPFA:OPFB:OPFC:OPFF:int 3ALIGNXMMOPTABdd OP00, OP01, OP02, OP03, OP04, OP05, OP06, OP07, OP08, OP09, OP0A, OP0B, OP0C, OP0D, OP0E, OP0FddOP10, OP11, OP12, OP13, OP14, OP15, OP16, OP17, OP18, OP19, OP1A, OP1B, OP1C, OP1D, OP1E, OP1FddOP20, OP21, OP22, OP23, OP24, OP25, OP26, OP27, OP28, OP29, OP2A, OP2B, OP2C, OP2D, OP2E, OP2FddOP30, OP31, OP32, OP33, OP34, OP35, OP36, OP37, OP38, OP39, OP3A, OP3B, OP3C, OP3D, OP3E, OP3FddOP40, OP41, OP42, OP43, OP44, OP45, OP46, OP47, OP48, OP49, OP4A, OP4B, OP4C, OP4D, OP4E, OP4FddOP50, OP51, OP52, OP53, OP54, OP55, OP56, OP57, OP58, OP59, OP5A, OP5B, OP5C, OP5D, OP5E, OP5FddOP60, OP61, OP62, OP63, OP64, OP65, OP66, OP67, OP68, OP69, OP6A, OP6B, OP6C, OP6D, OP6E, OP6FddOP70, OP71, OP72, OP73, OP74, OP75, OP76, OP77, OP78, OP79, OP7A, OP7B, OP7C, OP7D, OP7E, OP7FddOP80, OP81, OP82, OP83, OP84, OP85, OP86, OP87, OP88, OP89, OP8A, OP8B, OP8C, OP8D, OP8E, OP8FddOP90, OP91, OP92, OP93, OP94, OP95, OP96, OP97, OP98, OP99, OP9A, OP9B, OP9C, OP9D, OP9E, OP9FddOPA0, OPA1, OPA2, OPA3, OPA4, OPA5, OPA6, OPA7, OPA8, OPA9, OPAA, OPAB, OPAC, OPAD, OPAE, OPAFddOPB0, OPB1, OPB2, OPB3, OPB4, OPB5, OPB6, OPB7, OPB8, OPB9, OPBA, OPBB, OPBC, OPBD, OPBE, OPBFddOPC0, OPC1, OPC2, OPC3, OPC4, OPC5, OPC6, OPC7, OPC8, OPC9, OPCA, OPCB, OPCC, OPCD, OPCE, OPCFddOPD0, OPD1, OPD2, OPD3, OPD4, OPD5, OPD6, OPD7, OPD8, OPD9, OPDA, OPDB, OPDC, OPDD, OPDE, OPDFddOPE0, OPE1, OPE2, OPE3, OPE4, OPE5, OPE6, OPE7, OPE8, OPE9, OPEA, OPEB, OPEC, OPED, OPEE, OPEFddOPF0, OPF1, OPF2, OPF3, OPF4, OPF5, OPF6, OPF7, OPF8, OPF9, OPFA, OPFB, OPFC, OPFD, OPFE, OPFFALIGNXMMPollInt:mov eax, dwot[int_Pending] ;U - load Pending signal and eax, 3 ;V - clr bits leaecx, [ecx];U - jmp dwot[INT_TAB+eax*4] ;V - decode interruptALIGNXMMIRQ_:and eax, 1 ;U - clr NMI flag ... mov ecx, $s ;V - load S stack and ecx, 0FFh ;U - clr bits leaedx,[edx];V - mov dwot[int_Pending], eax ;U - write back Pending_intmov wot[ecx+ram+0100h-1], si;V - push now PC and ebx, 0EFh ;U - clr B flag ... add ebp, INT_C;V - add INT Cycles mov byt[ecx+ram+0100h-2], bl;U - push Flags sub cl, 3;V - sub Stack or ebx, I_FLAG;U - set Interrupt Disable Flagsmov eax, dwot[cpu_banks+28];V - get last Bankmov $s, ecx;U - write back Stack mov si, wot[eax+01FFEh] ;V - /N set IRQ addr jmp main_Loop;N - ALIGNXMMNMI_:and eax, 1 ;U - clr NMI flag ... mov ecx, $s ;V - load S stack and ecx, 0FFh ;U - clr bits leaedx,[edx];V - mov dwot[int_Pending], eax ;U - write back Pending_intmov wot[ecx+ram+0100h-1], si;V - push now PC and ebx, 0EFh ;U - clr B flag ... add ebp, INT_C;V - add INT Cycles mov byt[ecx+ram+0100h-2], bl;U - push Flags sub cl, 3;V - sub Stack or ebx, I_FLAG;U - set Interrupt Disable Flagsmov eax, dwot[cpu_banks+28];V - get last Bankmov $s, ecx;U - write back Stack mov si, wot[eax+01FFAh] ;V - /N set NMI addr jmp main_Loop;N - ALIGNXMMNO_DEAL:jmp main_LoopINT_TAB dd NO_DEAL, IRQ_, NMI_, NMI_ exec2a03 endpset_NMI proc C option prologue:none, epilogue:none or dwot[int_Pending], NMI_FLAG ret set_NMI endpsetIRQ proc C option prologue:none, epilogue:none or dwot[int_Pending], IRQ_FLAG ret setIRQ endpfastNMI proc C option prologue:none, epilogue:none fastNMI endpfastIRQ proc C option prologue:none, epilogue:none fastIRQ endpcpu_Reset proc C option prologue:none, epilogue:none push ebx lea edi, regs xor ecx, ecx or $p, 022h mov $a, ecx mov $x, ecx mov $y, ecx mov $s, 0FFh mov eax, dwot[cpu_banks+28] mov ecx, dwot[eax+01FFCh] ; set RESET addr mov $pc, ecx pop ebx retcpu_Reset endpset_DMA_Cycles proc C option prologue:none, epilogue:none test dword ptr[esp+4], -1 je __No_Forcemov dwot[regs+024], 514__No_Force:add dwot[regs+024], 514retset_DMA_Cycles endpend 0 0
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