Chapter 4-02

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4.1.4 Y86 Exceptions
The possible values for status code Stat (describing the overall state of the executing program) are shown in Figure 4.5.
Code 3 ADR indicates that the processor attempted to read from or write to an invalid memory address, either while fetching an instruction or while reading or writing data. We limit the maximum address and any access to an address beyond this limit will trigger an ADR exception.

In a more complete design, the processor would typically invoke an exception handler, a procedure designated to handle the specific type of exception encountered.
4.1.5 Y86 Programs



Words beginning with “.” are assembler directives telling the assembler to adjust the address at which it is generating code or to insert some words of data.
The directive .pos 0 (line 2) indicates that the assembler should begin generating code starting at address 0. This is the starting address for all Y86 programs.
The next two instructions (lines 3 and 4) initialize the stack and frame pointers. The label Stack is declared at the end of the program (line 47), to indicate address 0x100 using a .pos directive (line 46).

Lines 9 to 13 of the program declare an array of four words, having values 0xd, 0xc0, 0xb00, and 0xa000. The label array denotes the start of this array, and is aligned on a 4-byte boundary (using the .align directive).

We have implemented an instruction set simulator we call yis, the purpose of which is to model the execution of a Y86 machine-code program. Running on our sample object code, yis generates the following output:

The first line of the simulation output summarizes the execution and the resulting values of the PC and program status. In printing register and memory values, it only prints out words that change during simulation, either in registers or in memory. The original values (here they are all zero) are shown on the left, and the final values are shown on the right. Register %eax contains 0xabcd, the sum of the four-element array passed to subroutine Sum. The stack, which starts at address 0x100 and grows toward lower addresses, has been used, causing changes to words of memory at addresses 0xe8 through 0xfc. This is well away from 0x7c, the maximum address of the executable code.
4.1.6 Some Y86 Instruction Details
pushl %esp: push the original value of %esp, not push the decremented value of %esp.
popl %esp sets the stack pointer to the value read from memory. It is equivalent to the instruction: mrmovl (%esp),%esp.
4.2 Logic Design and the Hardware Control Language HCL
4.3 Sequential Y86 Implementations
4.3.1 Organizing Processing into Stages
We organize operations in a sequence of stages, attempting to make all instructions follow a uniform sequence, even though the instructions differ greatly in their actions. The following is an informal description of the stages and the operations performed within them:

Fetch:
The fetch stage reads the bytes of an instruction from memory, using the program counter (PC) as the memory address. From the instruction it extracts the two 4-bit portions of the instruction specifier byte, referred to as icode (the instruction code) and ifun (the instruction function).
It possibly fetches a register specifier byte, giving one or both of the register operand specifiers rA and rB. It also possibly fetches a 4-byte constant word valC.
It computes valP to be the address of the instruction following the current one in sequential order. valP equals the value of the PC plus the length of the fetched instruction.
Decode:
The decode stage reads up to two operands from the register file, giving values valA and/or valB. Typically, it reads the registers designated by instruction fields rA and rB, but for some instructions it reads register %esp.
Execute:
In the execute stage, the arithmetic/logic unit (ALU) either performs the operation specified by the instruction, computes the effective address of a memory reference, or increments or decrements the stack pointer. We refer to the resulting value as valE. The condition codes are possibly set. For a jump instruction, the stage tests the condition codes and branch condition (given by ifun) to see whether or not the branch should be taken.
Memory:
The memory stage may write data to memory, or it may read data from memory. We refer to the value read as valM.
Write back:
The write-back stage writes up to two results to the register file.
PC update:
The PC is set to the address of the next instruction.
The processor loops indefinitely, performing these stages. In our simplified implementation, the processor will stop when any exception occurs: it executes a halt or invalid instruction, or it attempts to read or write an invalid address. In a more complete design, the processor would enter an exception-handling mode and begin executing special code determined by the type of exception.


Four integer operations (addl, subl, andl, and xorl) all have the same value of icode. We can handle them all by an identical sequence of steps, except that the ALU computation must be set according to the particular instruction operation, encoded in ifun.
Fetch stage, we do not require a constant word, and so valP is computed as PC + 2. Decode stage, we read both operands. These are supplied to the ALU in the execute stage, along with the function specifier ifun, so that valE becomes the instruction result. Nothing happens in the memory stage for these instructions, but valE is written to register rB in the write-back stage, and the PC is set to valP to complete the instruction execution.

The subl instruction on line 3: the previous two instructions initialize registers %edx and %ebx to 9 and 21, respectively; and the instruction is located at address 0x00c and consists of 2 bytes, having values 0x61 and 0x23.

We achieve the desired effect of setting register %ebx to 12, setting all three condition codes to zero, and incrementing the PC by 2.


Line 6: We have 9 in register %edx and 128 in register %esp and the instruction is located at address 0x01a and consists of 2 bytes having values 0xa0 and 0x28.

The instruction has the effect of setting %esp to 124, writing 9 to address 124, and incrementing the PC by 2.


jXX: Execute stage: we check the condition codes and the jump condition to determine whether or not to take the branch, yielding a 1-bit signal Cnd. During the PC update stage, we test this flag, and set the PC to valC (the jump target) if the flag is 1, and to valP (the address of the following instruction) if the flag is 0.

Line 8: The condition codes were all set to zero by the subl instruction (line 3), and so the branch will not be taken. The instruction is located at address 0x01e and consists of 5 bytes. The first has value 0x73, while the remaining 4 bytes are 0x00000028, the jump target.


With instruction call, we push valP, the address of the instruction that follows the call instruction. During the PC update stage, we set the PC to valC, the call destination.
With instruction ret, we assign valM, the value popped from the stack, to the PC in the PC update stage.

Line 13: The previous call instruction set %esp to 124 and stored the return address 0x028 at memory address 124.

The instruction has the effect of setting the PC to 0x028, the address of the halt instruction. It also sets %esp to 128.
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