vhdl的描述

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以二选一多路选择器为例

（1）行为描述

只考虑电路的功能和行为

当S为0时选择A，当S为1时选择B

library ieee;use ieee.std_logic_1164.all;entity mux21_1 isport(A,B: in std_logic;--A，B输入信号S: in std_logic;--选择信号Y: out std_logic);--输出信号end entity mux21_1;architecture arch of mux21_1 isbegin process(A, B, S)beginif S = '0' thenY <= A;elseY <= B;end if;end process;end architecture arch;

（2）数据流描述

考虑输入与输出之间的逻辑关系

library ieee;use ieee.std_logic_1164.all;entity mux21_2 isport(A,B: in std_logic;S: in std_logic;Y: out std_logic);end mux21_2;architecture arch of mux21_2 isbeginprocess(A,B,S)beginY <= ((not S) and A) or (S and B);end process;end architecture arch;

（3）结构描述

二选一多路选择器有非、与、或构成

library ieee;use ieee.std_logic_1164.all;entity and21 isport(DIN1,DIN2: in std_logic;DOUT: out std_logic);end entity and21;architecture arch of and21 isbeginDOUT <= DIN1 and DIN2;end architecture arch;--------------------------------------library ieee;use ieee.std_logic_1164.all;entity not21 isport(DIN: in std_logic;DOUT: out std_logic);end entity not21;architecture arch of not21 isbeginDOUT <= (not DIN);end architecture arch;---------------------------------------library ieee;use ieee.std_logic_1164.all;entity or21 isport(DIN1, DIN2: in std_logic;DOUT: out std_logic);end entity or21;architecture arch of or21 isbeginDOUT<= DIN1 or DIN2;end architecture arch;----------------------------------------library ieee;use ieee.std_logic_1164.all;entity mux21_3 isport(A,B: in std_logic;S: in std_logic;Y: out std_logic);end entity mux21_3;architecture arch of mux21_3 iscomponent and21 port(DIN1,DIN2: in std_logic;DOUT: out std_logic);end component;component or21port(DIN1, DIN2: in std_logic;DOUT: out std_logic);end component;component not21 port(DIN: in std_logic;DOUT: out std_logic);end component;signal temp1, temp2, temp3, temp4: std_logic;beginu1: not21 port map(S, temp1);u2: and21 port map(A, temp1, temp2);u3: and21 port map(B, S, temp3);u4: or21 port map(temp2, temp3, Y);end architecture arch;

（4）混合描述

前三种方式混合描述

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