Vivado AXI Reference Guide 阅读笔记

本文是UG1037 Vivado AXI Reference Guide的阅读摘抄笔记，希望帮助大家迅速了解AXI。

Introducing AXI 

AXI4 interfaces有三种类型:

•AXI4: For high-performance memory-mapped requirements.
• AXI4-Lite: For simple, low-throughput memory-mapped communication (for example,
to and from control and status registers).
• AXI4-Stream: For high-speed streaming data.

更加详细点的介绍：

AXI4 is for memory-mapped interfaces and allows high throughput bursts of up to 256 data transfer cycles with just a single address phase.
° AXI4-Lite is a light-weight, single transaction memory-mapped interface. It has a small logic footprint and is a simple interface to work with both in design and
usage.
° AXI4-Stream removes the requirement for an address phase altogether and allows unlimited data burst size. AXI4-Stream interfaces and transfers do not have address phases and are therefore not considered to be memory-mapped.


At a hardware level, AXI4 allows systems to be built with a different clock for each AXI master-slave pair. In addition, the AXI4 protocol allows the insertion of register slices (often called pipeline stages) to aid in timing closure.

IMPORTANT: Unlike AXI4, you cannot reorder AXI4-Stream transfers.

Memory-Mapped Protocols: In memory-mapped protocols (AXI3, AXI4, and AXI4-Lite), all transactions involve the concept of transferring a target address within a system memory space and data.

AXI4-Stream是我要重点研究的，会用到。性能虽好，看来使用会复杂很多

AXI4-Stream Protocol: Use the AXI4-Stream protocol for applications that typically focus on a data-centric and data-flow paradigm where the concept of an address is not present or not required. Each AXI4-Stream acts as a single unidirectional channel with a handshaking data flow.
At this lower level of operation (compared to the memory-mapped protocol types), the mechanism to move data between IP is defined and efficient, but there is no unifying address context between IP. The AXI4-Stream IP can be better optimized for performance in data flow applications, but also tends to be more specialized around a given application space.

Data Interpretation
IMPORTANT: The AXI protocol does not specify or enforce the interpretation of data; therefore, you need to understand the data contents, and the different IP must have a compatible interpretation of the data.

一些AXI例程的视频资源
VIDEO:
Packaging Custom IP for use with IP Integrator,
Creating an AXI Peripheral in Vivado,
Designing with Vivado IP Integrator,
Targeting Zynq Using Vivado IP Integrator,
Using UltraScale Memory Controller IP,
AXI PCI Express MIG Subsystem Built in IP Integrator, and
Specifying AXI4-Lite Interfaces for your Vivado System Generator Design.

想要用好zynq了解axi是必须的！