ARM PROCESSOR FUNDAMENTALS（arm处理器基础）

本文介绍了ARM处理器的基础概要，如果兴趣的朋友可以去参考英文原著《ARM System Developer’s Guide》
本文包含7个部分，包括ARM寄存器，ARM 当前程序状态寄存器，Pipeline，异常中断与向量表，核心扩展，和最后ARM核心修订以及家族的介绍

1-Registers(寄存器)

• 一共16个常用寄存器，R0~R15（r13-sp,r14-lr,r15-pc ）
• cpsr(current program status register)

2-CURRENT PROGRAM STATUS REGISTER-CPSR-

2-1 banked register

• 20 registers are hidden from a program at times
• SPSR（saved program status register）

2-2 State and instruction sets

• ARM,Thumb，jazelle

2-3 INTERRUPT MASK

2-4 CONDITION FLAGS

• This particular subtract instruction specifically updates the cpsr

2-5 CONDITIONAL EXECUTION

• The processor compares the condition attribute with the condition flags in the cpsr.If they match, then the instruction is executed

3-PIPELINE

核心：execute an instruction every cycle

• Code written for the ARM7 will execute on an ARM9 or ARM10
• ARMx中的pipeline

ARMx Pipeline ARM7 3-stage ARM9 5-stage ARM10 6-stage

3-1pipeline execution characteristics

• arm7:pc + two instructions ahead
• brach, arm core will flush the pipeline
• ARM10 use branch prediction
• 一个指令在execute stage的时候，遇到中断也会完成运行。其他在pipeline的指令会被遗弃。完成中断后，会重新填充pipeline

4-exceptions-interrupts-and the vector table

• 遇到异常和中断的时候，会set pc到特殊的内存地址（在vector table中）

5-core extensions

5-1memory management

1.no protection
2.MPU(memory protection unit)提供有限的保护
3.MMU(memory management unit)full protection,支持multitasking

5-2 TCM-tightly couple memory和Cache

1. cache缓存data和instruction
2. TCM is a fast SRAM.位于接近核心的位置，监视cycle执行时间，对实时系统需要确定性的数据有重要作用。

6-architecture revisions

ARM7 TDII后均有TDMI