JLink、JTAG接口详细图解
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说明:
1脚:通常连接到目标板的vdd,用来检测目标系统是否供电;检测原理上图中有简单的说明。
2脚:原版的JLink这个引脚没有使用,不提供Vsupply输出,而很多改造版的JLink通过跳线选择从该引脚输出3.3V的电压给外边,我的就是这样的。
可以到网上找JLink的原理图看看。
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0517b/Cjaeccji.html
JTAG interface signals
The following table describes the signals on the JTAG interfaces:
Table
DBGACK
-
This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system. It is recommended that this signal is pulled LOW on the target.
DBGRQ
-
This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. The RVI software maintains this signal as LOW.
When applicable,RVI uses the scan chain 2 of the processor to put the processor in debug state. It is recommended that this signal is pulled LOW on the target.
GND
-
Ground.
nSRST
Input/output
Active Low output from RVI to the target system reset, with a 4.7kΩ pull-up resistor for de-asserted state. This is also an input to RVI so that a reset initiated on the target can be reported to the debugger.
This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.
nTRST
Output
Active Low output from RVI to the Reset signal on the target JTAG port, driven to the VTref voltage for de-asserted state. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.
RTCK
Input
Return Test Clock signal from the target JTAG port to RVI. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed,
RTCK
TCK
Output
Test Clock signal from RVI to the target JTAG port. It is recommended that this pin is pulled LOW on the target.
TDI
Output
Test Data In signal from RVI to the target JTAG port. It is recommended that this pin is pulled HIGH on the target.
TDO
Input
Test Data Out from the target JTAG port to RVI. It is recommended that this pin is pulled HIGH on the target.
TMS
Output
Test Mode signal from RVI to the target JTAG port. This pin must be pulled HIGH on the target so that the effect of any spurious
Vsupply
Input
This pin is not connected in the RVI unit. It is reserved for compatibility with other equipment to be used as a power feed from the target system.
VTref
Input
This is the target reference voltage. It indicates that the target has power, and It must be at least 0.628V.
另外电源的连线也需要加以额外考虑,因为Dragon-ICE要从目标板上吸取超过100mA的大电流。最好能有专门的敷铜层来供电,假如只能使用连线供电的话,最小线宽不应小于10mil (0.254mm)。
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