system_stm32f10x.c（V3.5.0）解读

  ******************************************************************************  * @file    system_stm32f10x.c  * @author  MCD Application Team  * @version V3.5.0  * @date    11-March-2011  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.  *   * 1.  This file provides two functions and one global variable to be called from   *     user application:  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier  *                      factors, AHB/APBx prescalers and Flash settings).   *                      This function is called at startup just after reset and   *                      before branch to main program. This call is made inside  *                      the "startup_stm32f10x_xx.s" file.  *  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used  *                                  by the user application to setup the SysTick   *                                  timer or configure other parameters.  *                                       *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must  *                                 be called whenever the core clock is changed  *                                 during program execution.  *  * 2. After each device reset the HSI (8 MHz) is used as system clock source.  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to  *    configure the system clock before to branch to main program.  *  * 3. If the system clock source selected by user fails to startup, the SystemInit()  *    function will do nothing and HSI still used as system clock source. User can   *    add some code to deal with this issue inside the SetSysClock() function.  *  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.   *    When HSE is used as system clock source, directly or through PLL, and you  *    are using different crystal you have to adapt the HSE value to your own  *    configuration.  *          ******************************************************************************

由第2条可以得知，单片机一上电或复位，以8M的HSI运行，之后执行函数SystemInit ()，此函数的功能主要是复位与时钟相关的寄存器，并执行SetSysClock（）。

#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)/* #define SYSCLK_FREQ_HSE    HSE_VALUE */ #define SYSCLK_FREQ_24MHz  24000000#else/* #define SYSCLK_FREQ_HSE    HSE_VALUE *//* #define SYSCLK_FREQ_24MHz  24000000 */ /* #define SYSCLK_FREQ_36MHz  36000000 *//* #define SYSCLK_FREQ_48MHz  48000000 *//* #define SYSCLK_FREQ_56MHz  56000000 */#define SYSCLK_FREQ_72MHz  72000000#endif

由此部分代码可知，默认状态下，在函数SetSysClock（）中将会执行函数SetSysClockTo72()。

  if (HSEStatus == (uint32_t)0x01)  {    /* Enable Prefetch Buffer */    FLASH->ACR |= FLASH_ACR_PRFTBE;    /* Flash 2 wait state */    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;        /* HCLK = SYSCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;    /* PCLK2 = HCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;    /* PCLK1 = HCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;#ifdef STM32F10X_CL    /* Configure PLLs ------------------------------------------------------*/    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);    /* Enable PLL2 */    RCC->CR |= RCC_CR_PLL2ON;    /* Wait till PLL2 is ready */    while((RCC->CR & RCC_CR_PLL2RDY) == 0)    {    }    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |                             RCC_CFGR_PLLMULL9); #else        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |                                        RCC_CFGR_PLLMULL));    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);#endif /* STM32F10X_CL */    /* Enable PLL */    RCC->CR |= RCC_CR_PLLON;    /* Wait till PLL is ready */    while((RCC->CR & RCC_CR_PLLRDY) == 0)    {    }    /* Select PLL as system clock source */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;        /* Wait till PLL is used as system clock source */    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)    {    }  }  else  { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */  }

此部分代码说明当HSE准备好之后，就会配置PLL，使PLLCLK位72MHz，之后等待system clock source切换至PLL。
在实际的时钟配置中，在else处设置调试断点，可确认外部时钟是否起振工作。