s5pv210 datasheet_system_VECTORED INTERRUPT CONTROLLER

1 VECTORED INTERRUPT CONTROLLER
1.1 OVERVIEW OF VECTORED INTERRUPT CONTROLLER
The interrupt controller in S5PV210 is composed of four Vectored Interrupt Controller (VIC), ARM PrimeCell
PL192 and four TrustZone Interrupt Controller (TZIC), SP890.
Four TZIC’s and four VIC’s are daisy-chained to support up to 93 interrupt sources. The TZIC provides a software
interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ interrupt and
masks the interrupt source(s) from the interrupt controller on the non-secure side of the system (VIC). Use the
latter to generate nIRQ signal.

To generate nFIQ from the non-secure interrupt sources, the TZIC0 takes the nNSFIQIN signal from the nonsecure interrupt controller.

中断控制器在S5PV210是由四个向量中断控制器（VIC），ARM PrimeCell

pl192 TrustZone中断控制器（tzic），sp890。

四个tzic和四个VIC的链接一起支持多达93个中断源。

tzic提供在TrustZone安全中断系统设计一个软件接口设计。它提供了安全的NFIQ控制中断

掩蔽从中断控制器的非安全方面的系统（VIC）的中断源（S）。使用后者产生nirq信号。

生成NFIQ从非安全的tzic0中断源，TZIC0获得的nnsfiqin信号来自非安全的中断控制器。

1.1.1 KEY FEATURES OF VECTORED INTERRUPT CONTROLLER
• Supports 93 vectored IRQ interrupts
• Fixed hardware interrupts priority levels
• Programmable interrupt priority levels
• Supports Hardware interrupt priority level masking
• Programmable interrupt priority level masking
• Generates IRQ and FIQ
• Generates Software interrupt
• Test registers
• Raw interrupt status
• Interrupt request status
• Supports Privileged mode for restricted access

•支持93向量IRQ中断

•固定硬件中断优先级

•可编程中断优先级

•支持硬件中断优先级的屏蔽

•可编程中断优先级掩蔽

•产生IRQ和FIQ

•生成软件中断

•测试寄存器

•原中断状态

•中断请求状态

•支持限制访问特权模式