跨时钟域处理-flag
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转载自http://www.fpga4fun.com/CrossClockDomain2.html
A flag to another clock domain
If the signal that needs to cross the clock domains is just a pulse (i.e. it lasts just one clock cycle), we call it a "flag". The previous design usually doesn't work (the flag might be missed, or be seen for too long, depending on the ratio of the clocks used).
We still want to use a synchronizer, but one that works for flags.
The trick is to transform the flags into level changes, and then use the two flip-flops technique.
module Flag_CrossDomain( input clkA, input FlagIn_clkA, input clkB, output FlagOut_clkB);// this changes level when the FlagIn_clkA is seen in clkAreg FlagToggle_clkA;always @(posedge clkA) FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;// which can then be sync-ed to clkBreg [2:0] SyncA_clkB;always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};// and recreate the flag in clkBassign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);endmodule
Now if you want the clkA domain to receive an acknowledgment (that clkB received the flag), just add a busy signal.
module FlagAck_CrossDomain( input clkA, input FlagIn_clkA, output Busy_clkA, input clkB, output FlagOut_clkB);reg FlagToggle_clkA;always @(posedge clkA) FlagToggle_clkA <= FlagToggle_clkA ^ (FlagIn_clkA & ~Busy_clkA);reg [2:0] SyncA_clkB;always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};reg [1:0] SyncB_clkA;always @(posedge clkA) SyncB_clkA <= {SyncB_clkA[0], SyncA_clkB[2]};assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);assign Busy_clkA = FlagToggle_clkA ^ SyncB_clkA[1];endmodule
Now if you want the clkA domain to receive an acknowledgment (that clkB received the flag), just add a busy signal.
module FlagAck_CrossDomain( input clkA, input FlagIn_clkA, output Busy_clkA, input clkB, output FlagOut_clkB);reg FlagToggle_clkA;always @(posedge clkA) FlagToggle_clkA <= FlagToggle_clkA ^ (FlagIn_clkA & ~Busy_clkA);reg [2:0] SyncA_clkB;always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};reg [1:0] SyncB_clkA;always @(posedge clkA) SyncB_clkA <= {SyncB_clkA[0], SyncA_clkB[2]};assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);assign Busy_clkA = FlagToggle_clkA ^ SyncB_clkA[1];endmodule
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