orr r0,r0,#R1_nF:OR:R1_iA

在S3C2440手册上时钟与电源管理有一部分内容如下： 

1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK. 

2. If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions(S3C2440 does not support synchronous bus mode). 

MMU_SetAsyncBusMode

mrc p15,0,r0,c1,c0,0

orr r0,r0,#R1_nF:OR:R1_iA

mcr p15,0,r0,c1,c0,0 

If HDIVN is not 0 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK. This feature can be used to change the CPU frequency as a half or more without affecting the HCLK and PCLK.

 

其它的内容在此不做解释，只解释一下“orr r0,r0,#R1_nF:OR:R1_iA”是什么意思。

参考手册“ARM920T(Rev 1)Technical Reference Manual”，有如下内容： 

Register 1, control register (orr r0,r0,#R1_nF:OR:R1_iA)

This register contains the control bits of the ARM920T. All reserved bits must either be written with 0 or 1, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. Use the following instructions to read and write this register:

MRC p15, 0, Rd, c1, c0, 0 ; read control register

MCR p15, 0, Rd, c1, c0, 0 ; write control register

 

Register bits

31  iA bit Asynchronous clock select

30 nF bit notFastBus select

29:15 Reserved Read

14 RR bit Round robin replacement

13 V bit Base location of exception registers

12 I bit ICache enable

11:10 Reserved

9 R bit ROM protection

8 S bit System protection

7 B bit Endianness

6:3 Reserved

2 C bit DCache enable

1 A bit Alignment fault enable

0 M bit MMU enable

 

Clocking modeiAnFFastBus mode 01Synchronous01Reserved10Asynchronous11

 

其中[31:30]bit是与“FastBus mode/Asynchronous”相关的。如果要切换到“Asynchronous”模式，则“iA=1;nF=1”，所以“#R1_nF:OR:R1_iA”就表示“0xc0000000”。