[USF-XSim-62] 'compile' step failed with error(s) while executing 'I

• module test( );
  reg clock;
  reg rst;
  reg button;
  wire led;
  
  
  FSM u1(
      .clock_100M(clock),
      . rst(rst),
     . button(button),
      .led(led)    
  );
  always
  #10 clock=~clock;
  
  
  initial
  begin
  
  
  end
  
  
  endmodule

当这样实例化对象时会出现下面的错误

• [USF-XSim-62] 'compile' step failed with error(s) while executing 'I:/Vivado_project/FSM/FSM.sim/sim_1/behav/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.

修改为下面这种方式，则能够仿真通过

module test( );
reg clock;
reg rst;
reg button;
wire led;

FSM u1(
    clock,
     rst,
    button,
    led    
);
always
#10 clock=~clock;

initial
begin

end

endmodule