学习FPGA过程中遇到的问题：QuartusII

在做包文练习时遇到的错误：
Error (10200): Verilog HDL Conditional Statement error at baowen3.v(130): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
错误的代码段出现在

  //dout_err    always  @(posedge clk or negedge rst_n)begin        if(rst_n==1'b0)begin            dout_err <= 0;        end        if(din_vld == 1'b1)begin//错误出现在这里            if(flag==1 && din_sop==1 && din_eop==1)begin                dout_err <= 1;            end             else if(flag==0 && din_sop==0 /*&& din_vld==1*/ && din_eop==1)begin                dout_err <= 1;            end            else if(din_err==1 && din_eop)begin                dout_err <= 1;            end            else if(flag_err==1 && din_eop==1)begin                dout_err <= 1;            end            else                dout_err <= 0;        end        else begin            dout_err <= 0;        end    end

Altera官方给出的解释
Error: Verilog HDL Conditional Statement error at : If-Else Statement does not match any sensitivity list edge
Description
This error may occur if you are trying to model a DFF with multiple control signals. The Quartus® II software will only infer a secondary signal from a single secondary signal in an IF condition. For example, you may have written the following sample structure to model a DFF primitive that can be reset by two signals, rst1 or rst2:
always @ (posedge clk or posedge rst1 or posedge rst2)

begin

if (rst1 == 1\’b1 || rst2 == 1\’b1)

q <= 1\'b0;  

else

q <= d; 

end

To correct this, edit the design to specify only one edge per if condition. For example, if you were to edit the previous example to specify only one edge per if condition, the Quartus II software would then succesfully recognize the DFF primitive. The sample code would then appear as follows:

always @ (posedge clk or posedge rst1 or posedge rst2)

begin

if (rst1 == 1\’b1)

q <= 1\'b0;    

else if (rst2 == 1\’b1)

q <= 1\'b0;

else

q <= d;  

end

Alternatively, you could generate the OR of rst1 and rst2 outside the Always construct.

This limitation will be addressed in a future version of the Quartus II software.
于是将
if(din_vld == 1’b1)begin
改成
else if(din_vld == 1’b1)begin
错误解决。