串口通信Usart发送程序

使用Verilog代码编写的USART发送程序：

数据位8位，停止位1位，校验位没有，流控没有

波特率由波特率模块生成

串口时序大致如下图所示：

module uart_trans(GClk,clk_bps,reset,tx_en,datain,Txd,tx_ok);input GClk,clk_bps,reset,tx_en;//全局时钟，波特率时钟，全局复位，发送启动信号input [7:0]datain;output Txd,tx_ok;//tx_en:__/^\____________________wire clk_bps;reg Txd,tx_ok;reg [7:0]data;//数据缓存reg [3:0]BitPos;//状态位reg tx_en0,tx_en1,tx_en2;    //rx_int信号寄存器，捕捉下降沿滤波用always @ (posedge GClk or negedge reset)     if(!reset) begin        tx_en0 <= 1'b0;        tx_en1 <= 1'b0;        tx_en2 <= 1'b0;    end    else begin        tx_en0 <= tx_en;        tx_en1 <= tx_en0;        tx_en2 <= tx_en1;    endassign pos_tx_en =  tx_en & ~tx_en0;    //捕捉到下降沿后，neg_rx_int拉高保持一个主时钟周期 reg TxAv;//发送有效信号，其控制信号具有优先级always @(posedge GClk or negedge reset)beginif(!reset) begin//当接收寄存器读时，位有效信号复位TxAv <= 1'b0;endelse if(tx_en)//接收模块接收到数据，立即发送出去pos_tx_enTxAv <= 1'b1;else if(BitPos==4'd10)TxAv<= 1'b0;//发送模块发送完毕else TxAv<=TxAv;end//tx_en:__/^\____________________//tx_ok:___________________/^\____//TxAv:___/^^^^^^^^^^^^^^^\_______always @(posedge GClk or negedge reset)beginif(!reset) begin//当接收寄存器读时，位有效信号复位tx_ok<=1'b1;endelse if(BitPos==4'd10) begintx_ok<=1'b1;endelse begintx_ok<=1'b0;endend/* 读入数据 */always @(posedge GClk or negedge reset)beginif(!reset) begindata<=8'd0;endelse if((BitPos==4'd0)&(pos_tx_en))data<=datain;else data<=data;endalways @(posedge GClk or negedge reset)beginif(!reset) beginTxd <= 1'b1;BitPos<=4'd10;endelse if(TxAv) beginif(clk_bps) beginBitPos<=BitPos+1'b1;case(BitPos)4'd0: Txd <= 1'b0;//起始位4'd1: Txd <= data[0];//数据位 开始4'd2: Txd <= data[1];4'd3: Txd <= data[2];4'd4: Txd <= data[3];4'd5: Txd <= data[4];4'd6: Txd <= data[5];4'd7: Txd <= data[6];4'd8: Txd <= data[7];4'd9: Txd <= 1'b1;//数据结束位,1位4'd10:;default:;endcaseendelse beginif(BitPos==4'd10)BitPos<=4'd0;endendelse Txd <= 1'b1;endendmodule