在FPGA中使用Verilog实现I2C通信
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按照I2C标准的官方时序
可以看出时序看起来很简单,不过它严格的按照时序要求来传送数据,马虎不得的,特别是起始和停止的条件,起始必须要时钟线SCL为高电平时数据线SDA拉低;而停止时必须要时钟线SCL为高电平时数据线SDA拉高;中间的数据的每一位传送都是必须要求在时钟线SCL为高定平时完成;
Verilog HDL程序采用基于状态机的时序设计实现,I2C速度为100KHz,本人开发板的晶振20Mhz。代码有点长,就截取状态机部分好了
`define DEVICE_WRITE 8'b1010_1010 //the data;
reg[7:0] db_r;
parameter IDLE = 4'd0;
parameter START1 = 4'd1;
parameter DATA = 4'd2;
parameter ACK1 = 4'd3;
parameter STOP1 = 4'd11;
parameter STOP2 = 4'd12;
reg[3:0] cstate;
reg sda_r;
reg sda_link;
reg[3:0] num;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
cstate <= IDLE;
sda_r <= 1'b1;
sda_link <= 1'b0; //input
num <= 4'd0;
end
else
case (cstate)
IDLE: begin
sda_link <= 1'b1; //output
sda_r <= 1'b1;
db_r <= `DEVICE_WRITE;
cstate <= START1;
end
START1: begin
if(`SCL_HIG) begin
sda_r <= 1'b0;
cstate <= DATA;
num <= 4'd0;
end
else cstate <= START1;
end
DATA: begin
if(`SCL_LOW) begin
if(num == 4'd8) begin
num <= 4'd0;
sda_r <= 1'b1;
sda_link <= 1'b0; //(input)
cstate <= ACK1;
end
else begin
cstate <= DATA;
num <= num+1'b1;
case (num)
4'd0: sda_r <= db_r[7];
4'd1: sda_r <= db_r[6];
4'd2: sda_r <= db_r[5];