自定义IP里面的各个总线接口的定义

这里我选择的是第一种总线。

图中红线里面的就是总线接口。下面进行逐一翻译。

1、Bus2IP_Clk :Synchronization clock provided to the user logic. All IPIC signals are synchronous to this clock. It is identical to the input <bus>_Clk signal of the peripheral. No additional buffering is provided on the clock; it is passed through as is.

提供给用户逻辑模块（IP）的同步时钟。所有的IPIC信号都是以此为时钟。它和外部电路的输入信号<bus>_Clk是同一个信号。这个时钟没有额外的缓冲。。。

2、Bus2IP_Resetn:Active low reset for use by the user IP. It is a pass through of the S_AXI_ARESETN input

低电平复位用户IP核。通过S_AXI_ARESETN 输入进来

3、Bus2IP_Addr：Address bus to the user logic. It indicates the address of the requested read or write operation. It can be used for additional address decoding or as input to addressable memory devices.

4、Bus2IP_CS：Active high chip select bus. Assertion of a chip select indicates an active transaction request to the chip select's target address space. This is typically used for user logic memory space selection.

5、Bus2IP_RNW：Input signal to the user logic. It indicates the sense of a requested operation with the user logic. High is a read and low is a write. It is valid whenever at least one of the Bus2IP_CS bits is active.

6、Bus2IP_Data：Write data bus to the user logic. Write data is accepted by the user logic during a write operation by assertion of the write acknowledgement signal and the rising edge of the Bus2IP_Clk

7、Bus2IP_BE：Byte Enable qualifiers for the requested read or write operation to the user logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates that byte lanes 2 and 3 contain valid data.

8、Bus2IP_RdCE：Active high chip enable bus to the user logic. These chip enables are only asserted during active read transaction requests with the target address space and in conjunction with the corresponding sub-address within the space. These are typically used for user logic readable registers selection.

9、Bus2Ip_WrCE: Active high chip enable bus to the user logic. These chip enables are asserted only during active write transaction requests with the target address space and in conjunction with the corresponding sub-address within the space. Typically used for user logic writable registers selection.

10、IP2Bus_data:Output read data bus from the user logic; data is qualified with the assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk.

11、IP2Bus_RdAck:Active high read data qualifier providing the read acknowledgement from the user logic. Read data on the IP2Bus_Data bus is deemed valid at the rising edge of the Bus2IP_Clk and IP2Bus_RdAck asserted high by the user logic.

12、IP2Bus_WrAck：Active high write data qualifier providing the write acknowledgement from the user logic. Write data on the Bus2IP_Data bus is deemed accepted by the user logic at the rising edge of the Bus2IP_Clk and IP2Bus_WrAck asserted high by the user logic. For immediate acknowledgement (such as for a register write), this signal can be tied to '1'. Wait states can be inserted in the transaction by delaying the assertion of the acknowledgement.

13、IP2Bus_Error：Active high signal indicating the user logic has encountered an error with the requested operation. It is asserted in conjunction with the read/write acknowledgement signal(s).