打三拍上下边沿检测代码段

module verilog_lesson;/*reg trigger_r1, trigger_r2, trigger_r3;//wire pos_tri;//wire neg_tri;always @(posedge clk or posedge rst_n) beginif (rst_n) begin// resettrigger_r1 <= 1`b0;trigger_r2 <= 1`b0;trigger_r3 <= 1`b0;endelse begintrigger_r1 <= trigger;trigger_r2 <= trigger_r1;trigger_r3 <= trigger_r2;endendassign pos_tri = trigger_r2 & ~trigger_r3;assign neg_tri = ~trigger_r2 & trigger_r3;*/reg trigger;// wire pos_tri;// wire neg_tri;reg clk;reg rst_n;wire pos_tri;wire neg_tri;trigg trigg_m0(.clk(clk),.rst_n(rst_n),.trigger(trigger),.pos_tri(pos_tri),.neg_tri(neg_tri));localparamSTEP = 40;always #(STEP/2) clk = ~clk;initialbeginrst_n = 0;trigger = 0;clk = 0;#(STEP * 2) rst_n = 1;#(STEP * 4) trigger = 1;#(STEP * 8) trigger = 0;#(STEP * 12) trigger = 1;#(STEP * 16) trigger = 0;$finish;endendmodule/*对于TRIGG来说，INPUT和OUTPUT仅仅是他的输入和输出，并不需要再定义是REG或WIRE*/module trigg(input clk,input rst_n,input trigger,output pos_tri,output neg_tri);reg trigger_r1, trigger_r2, trigger_r3;//wire pos_tri;//wire neg_tri;always @(posedge clk or negedge rst_n) beginif (! rst_n) begin// resettrigger_r1 <= 0;trigger_r2 <= 0;trigger_r3 <= 0;endelse begintrigger_r1 <= trigger;trigger_r2 <= trigger_r1;trigger_r3 <= trigger_r2;endendassign pos_tri = trigger_r2 & ~trigger_r3;assign neg_tri = ~trigger_r2 & trigger_r3;endmodule