u-boot启动第一阶段(未完)
来源：互联网 发布：linux ndk 编译的so 编辑：程序博客网 时间：2024/06/05 23:55
可参考一下http://blog.csdn.net/qq_33160790/article/details/60965224
1.设置cpu为svc模式
b reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
2.关看门狗
uboot程序一般比较简单所以关闭看门狗
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
3.屏蔽中断
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
4.初始化sdram
5.设置栈
6.初始化时钟
7.代码从flash拷贝到sdram
8.清bss段
9.调用
start_armboot
/* * armboot - Startup Code for ARM920 CPU-core * * Copyright (c) 2001Marius Gr鰃er <mag@sysgo.de> * Copyright (c) 2002Alex Z黳ke <azu@sysgo.de> * Copyright (c) 2002Gary Jennejohn <gj@denx.de> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <config.h>#include <version.h>/* ************************************************************************* * * Jump vector table as in table 3.1 in [1] * ************************************************************************* */.globl _start_start:b resetldrpc, _undefined_instructionldrpc, _software_interruptldrpc, _prefetch_abortldrpc, _data_abortldrpc, _not_usedldrpc, _irqldrpc, _fiq_undefined_instruction:.word undefined_instruction_software_interrupt:.word software_interrupt_prefetch_abort:.word prefetch_abort_data_abort:.word data_abort_not_used:.word not_used_irq:.word irq_fiq:.word fiq.balignl 16,0xdeadbeef/* ************************************************************************* * * Startup Code (reset vector) * * do important init only if we don't start from memory! * relocate armboot to ram * setup stack * jump to second stage * ************************************************************************* */_TEXT_BASE:.wordTEXT_BASE.globl _armboot_start_armboot_start:.word _start/* * These are defined in the board-specific linker script. */.globl _bss_start_bss_start:.word __bss_start.globl _bss_end_bss_end:.word _end.globl FREE_RAM_ENDFREE_RAM_END:.word0x0badc0de.globl FREE_RAM_SIZEFREE_RAM_SIZE:.word0x0badc0de.globl PreLoadedONRAMPreLoadedONRAM:.word0#ifdef CONFIG_USE_IRQ/* IRQ stack memory (calculated at run-time) */.globl IRQ_STACK_STARTIRQ_STACK_START:.word0x0badc0de/* IRQ stack memory (calculated at run-time) */.globl FIQ_STACK_STARTFIQ_STACK_START:.word 0x0badc0de#endif/* * the actual reset code */reset://设置cpu为管理模式/* * set the cpu to SVC32 mode */mrsr0,cpsrbicr0,r0,#0x1forrr0,r0,#0xd3msrcpsr,r0/* turn off the watchdog */#if defined(CONFIG_S3C2400)# define pWTCON0x15300000# define INTMSK0x14400008/* Interupt-Controller base addresses */# define CLKDIVN0x14800014/* clock divisor register */#elif defined(CONFIG_S3C2410)# define pWTCON0x53000000# define INTMOD 0X4A000004# define INTMSK0x4A000008/* Interupt-Controller base addresses */# define INTSUBMSK0x4A00001C# define CLKDIVN0x4C000014/* clock divisor register */#endif#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)ldr r0, =pWTCON//关闭看门狗mov r1, #0x0str r1, [r0]/* * mask all IRQs by setting all bits in the INTMR - default */movr1, #0xffffffff//关中断ldrr0, =INTMSKstrr1, [r0]# if defined(CONFIG_S3C2410)ldrr1, =0x3ffldrr0, =INTSUBMSKstrr1, [r0]# endif#if 0/* FCLK:HCLK:PCLK = 1:2:4 *//* default FCLK is 120 MHz ! */ldrr0, =CLKDIVNmovr1, #3strr1, [r0]#endif#endif/* CONFIG_S3C2400 || CONFIG_S3C2410 *//* * we do sys-critical inits only at reboot, * not when booting from ram! */#ifndef CONFIG_SKIP_LOWLEVEL_INITadrr0, _start/* r0 <- current position of code *///cpu初始化ldrr1, _TEXT_BASE/* test if we run from flash or RAM */cmp r0, r1 /* don't reloc during debug */blnecpu_init_crit#endif/* Set up the stack *///设置栈stack_setup:ldrr0, _TEXT_BASE/* upper 128 KiB: relocated uboot */subr0, r0, #CFG_MALLOC_LEN/* malloc area */subr0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */#ifdef CONFIG_USE_IRQsubr0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)#endifsubsp, r0, #12/* leave 3 words for abort-stack */#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl clock_init//设置时钟#endif #ifndef CONFIG_SKIP_RELOCATE_UBOOTrelocate:/* relocate U-Boot to RAM *///把代码从flash读到sdram里面去adrr0, _start/* r0 <- current position of code */ldrr1, _TEXT_BASE/* test if we run from flash or RAM */cmp r0, r1 /* don't reloc during debug */beq clear_bssldrr2, _armboot_startldrr3, _bss_startsubr2, r3, r2/* r2 <- size of armboot */#if 1bl CopyCode2Ram/* r0: source, r1: dest, r2: size */#elseaddr2, r0, r2/* r2 <- source end address */copy_loop:ldmiar0!, {r3-r10}/* copy from source address [r0] */stmiar1!, {r3-r10}/* copy to target address [r1] */cmpr0, r2/* until source end addreee [r2] */blecopy_loop#endif#endif/* CONFIG_SKIP_RELOCATE_UBOOT */clear_bss://清bss段ldrr0, _bss_start/* find start of bss segment */ldrr1, _bss_end/* stop here */mov r2, #0x00000000/* clear */clbss_l:strr2, [r0]/* clear loop... */addr0, r0, #4cmpr0, r1bleclbss_lSetLoadFlag:/* Set a global flag, PreLoadedONRAM */adrr0, _start/* r0 <- current position of code */ldrr1, _TEXT_BASE/* test if we run from flash or RAM */cmp r0, r1 /* don't reloc during debug */ldr r2, =PreLoadedONRAMmov r3, #1streq r3, [r2]#if 0/* try doing this stuff after the relocation */ldr r0, =pWTCONmov r1, #0x0str r1, [r0]/* * mask all IRQs by setting all bits in the INTMR - default */movr1, #0xffffffffldrr0, =INTMRstrr1, [r0]/* FCLK:HCLK:PCLK = 1:2:4 *//* default FCLK is 120 MHz ! */ldrr0, =CLKDIVNmovr1, #3strr1, [r0]/* END stuff after relocation */#endifldrpc, _start_armboot_start_armboot:.word start_armboot//调用start_armboot/* ************************************************************************* * * CPU_init_critical registers * * setup important registers * setup memory timing * ************************************************************************* */#ifndef CONFIG_SKIP_LOWLEVEL_INITcpu_init_crit:/* * flush v4 I/D caches */movr0, #0mcrp15, 0, r0, c7, c7, 0/* flush v3/v4 cache */mcrp15, 0, r0, c8, c7, 0/* flush v4 TLB *//* * disable MMU stuff and caches */mrcp15, 0, r0, c1, c0, 0bicr0, r0, #0x00002300@ clear bits 13, 9:8 (--V- --RS)bicr0, r0, #0x00000087@ clear bits 7, 2:0 (B--- -CAM)orrr0, r0, #0x00000002@ set bit 2 (A) Alignorrr0, r0, #0x00001000@ set bit 12 (I) I-Cachemcrp15, 0, r0, c1, c0, 0/* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will * find a lowlevel_init.S in your board directory. */movip, lrbllowlevel_initmovlr, ipmovpc, lr#endif /* CONFIG_SKIP_LOWLEVEL_INIT *//* ************************************************************************* * * Interrupt handling * ************************************************************************* */@@ IRQ stack frame.@#define S_FRAME_SIZE72#define S_OLD_R068#define S_PSR64#define S_PC60#define S_LR56#define S_SP52#define S_IP48#define S_FP44#define S_R1040#define S_R936#define S_R832#define S_R728#define S_R624#define S_R520#define S_R416#define S_R312#define S_R28#define S_R14#define S_R00#define MODE_SVC 0x13#define I_BIT 0x80/* * use bad_save_user_regs for abort/prefetch/undef/swi ... * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling */.macrobad_save_user_regssubsp, sp, #S_FRAME_SIZEstmiasp, {r0 - r12}@ Calling r0-r12ldrr2, _armboot_startsubr2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)subr2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stackldmiar2, {r2 - r3}@ get pc, cpsraddr0, sp, #S_FRAME_SIZE@ restore sp_SVCaddr5, sp, #S_SPmovr1, lrstmiar5, {r0 - r3}@ save sp_SVC, lr_SVC, pc, cpsrmovr0, sp.endm.macroirq_save_user_regssubsp, sp, #S_FRAME_SIZEstmiasp, {r0 - r12}@ Calling r0-r12add r8, sp, #S_PCstmdb r8, {sp, lr}^ @ Calling SP, LRstr lr, [r8, #0] @ Save calling PCmrs r6, spsrstr r6, [r8, #4] @ Save CPSRstr r0, [r8, #8] @ Save OLD_R0movr0, sp.endm.macroirq_restore_user_regsldmiasp, {r0 - lr}^@ Calling r0 - lrmovr0, r0ldrlr, [sp, #S_PC]@ Get PCaddsp, sp, #S_FRAME_SIZEsubspc, lr, #4@ return & move spsr_svc into cpsr.endm.macro get_bad_stackldrr13, _armboot_start@ setup our mode stacksubr13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)subr13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stackstrlr, [r13]@ save caller lr / spsrmrslr, spsrstr lr, [r13, #4]movr13, #MODE_SVC@ prepare SVC-Mode@ msrspsr_c, r13msrspsr, r13movlr, pcmovspc, lr.endm.macro get_irq_stack@ setup IRQ stackldrsp, IRQ_STACK_START.endm.macro get_fiq_stack@ setup FIQ stackldrsp, FIQ_STACK_START.endm/* * exception handlers */.align 5undefined_instruction:get_bad_stackbad_save_user_regsbl do_undefined_instruction.align5software_interrupt:get_bad_stackbad_save_user_regsbl do_software_interrupt.align5prefetch_abort:get_bad_stackbad_save_user_regsbl do_prefetch_abort.align5data_abort:get_bad_stackbad_save_user_regsbl do_data_abort.align5not_used:get_bad_stackbad_save_user_regsbl do_not_used@ thisway.diy, 2006.06.24.globl Launch .align4Launch: mov r7, r0 @ diable interrupt@ disable watch dog timermovr1, #0x53000000movr2, #0x0strr2, [r1] ldr r1,=INTMSK ldr r2,=0xffffffff @ all interrupt disable str r2,[r1] ldr r1,=INTSUBMSK ldr r2,=0x7ff @ all sub interrupt disable str r2,[r1] ldr r1, = INTMOD mov r2, #0x0 @ set all interrupt as IRQ (not FIQ) str r2, [r1] @ movip, #0mcrp15, 0, ip, c13, c0, 0 @/* zero PID */mcrp15, 0, ip, c7, c7, 0 @/* invalidate I,D caches */mcrp15, 0, ip, c7, c10, 4 @/* drain write buffer */mcrp15, 0, ip, c8, c7, 0 @/* invalidate I,D TLBs */mrcp15, 0, ip, c1, c0, 0 @/* get control register */bicip, ip, #0x0001 @/* disable MMU */mcrp15, 0, ip, c1, c0, 0 @/* write control register */ @ MMU_EnableICache @mrc p15,0,r1,c1,c0,0 @orr r1,r1,#(1<<12) @mcr p15,0,r1,c1,c0,0 @ clear SDRAM: the end of free mem(has wince on it now) to the end of SDRAM ldr r3, FREE_RAM_END ldr r4, =PHYS_SDRAM_1+PHYS_SDRAM_1_SIZE @ must clear all the memory unused to zero mov r5, #0 ldr r1, _armboot_start ldr r2, =On_Steppingstone sub r2, r2, r1 mov pc, r2On_Steppingstone:2: stmia r3!, {r5} cmp r3, r4 bne 2b @ set sp = 0 on sys mode mov sp, #0 @ add by thisway.diy 2006.06.26, switch to SVC modemsrcpsr_c,#0xdf@ set the I-bit = 1, diable the IRQ interruptmsrcpsr_c,#0xd3@ set the I-bit = 1, diable the IRQ interrupt ldr sp, =0x31ff5800 nopnop nopnopmov pc, r7 @ Jump to PhysicalAddressnop mov pc, lr#ifdef CONFIG_USE_IRQ.align5irq:/* add by www.100ask.net to use IRQ for USB and DMA */sublr, lr, #4 @ the return addressldrsp, IRQ_STACK_START @ the stack for irqstmdbsp!, { r0-r12,lr }@ save registersldrlr,=int_return @ set the return addrldrpc, =IRQ_Handle @ call the isrint_return:ldmiasp!, { r0-r12,pc }^@ return from interrupt.align5fiq:get_fiq_stack/* someone ought to write a more effiction fiq_save_user_regs */irq_save_user_regsbl do_fiqirq_restore_user_regs#else.align5irq:get_bad_stackbad_save_user_regsbl do_irq.align5fiq:get_bad_stackbad_save_user_regsbl do_fiq#endif
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