Chapter 3 A top-level view of computer function and interconnection

1. von Neumann architecture:
   • Data and instructions are stored in a single read-write memory
   • The contents of this memory are addressable by location, without regard to the type of data contained there
   • Execution occurs in a sequential fashion(unless explicitly modified) from one instruction to the next
2. Computer main components
   • CPU
   • I/O
   • Main memory
   • System bus

3. Computer function
   • Basic function performed by a computer is execution of a program
   • The CPU time of processing an instruction is called instrucion cycle.
   • Instruction processing consists of two steps: The processor reads(fetches) instrctions from the memory one at a time and executes each instrction.
   • • instruction cycle = fetch cycle & execute cycle
4. Instruction fetch and execute
   1. The processot fetches an instruction from memory
   2. Unless told otherwise, the processor always increments the PC after each instruction fetch.
      • Length of PC should be calculated, however, it, in fact, equals to the length of AC/IR
   3. The fetched instruction is loaded into a register in the processor known as the instruction register(IR)
   4. The processor interprets the instruction and performs the required action:
      • Data transfer between CPU and main memory
      • Data transfer between CPU and I/O module
      • Some arithmetic or logical operation on data
      • Control
      • Combination of above

5. Flow of an Instruction
   • Instruction address calculation
   • Instruction fetch
   • Instruction operation decoding
   • operand address calculation
   • Operand fetch
   • Data operation
   • Operand storage

6. Interrupts: a mechanism allowing other module to break CPU executing sequence
   • To improve processing efficiency
   • To allow CPU to process urgent events
   • If interrupt is pending, the processor does the following:
   • • Suspend execution of the current program being executed andsave its context
     • Save current context of PC and other data
     • Set the PC to starting address of an interrupt handler routine
   • An interrupt cycle is added to instruction cycle
   • • After an instruction cycle,processor checks for interrupt, Indicated by an interrupt signal
     • If no interrupt, fetch next instruction
     • If interrupt :
     • • Suspend execution of current program
       • Save context
       • Set PC to start address of interrupt handler routine
       • Process interrupt
       • Restore context and continue interrupted program

7. Multiple interrupts: an interrupt handler is interrupted
   1. Disable interrupts
      • Easy, FIFO
   2. Define priorities
      • More common

8. I/O function
   1. An I/O module can exchange data directly with the processor
   2. In some cases, it is desirable to allow I/O exchanges to occur directly with memory---DMA
9. Interconnection structure
   • The collection of paths connecting the various modules is called the interconnection structure
10. Bus interconnection
    1. A bus is a communication pathway connecting two or more devices(shared transmission medium)
    2. Bus type
       1. System bus: A bus that connects major computer components is called a system bus
       2. Peripheral bus
       3. Internal bus
    3. Data bus: for moving data between system modules
       • The width of the data bus is a key factor in determining overall system performance
       • Machine word-length: The most binary bits which machine can process in the integer operation
       • Data bus width = Machine word-length = Register length
    4. Address bus: designate the source or destination of the data on the data bus
       • The width of the address bus determines the maximum possible memory capacity of the system
    5. Control line: to control the access to and the use of the data and address line
       • Memory read/write signal
       • I/O read/write
       • Transfer ACK
       • Bus Request
       • Bus grant
       • Interrupt request & ACK
       • Clock signals
       • Reset
11. Multiple-bus hierarchies
    1. If great number of devices are connected to the bus, performance will suffer
       1. greater bus length → greater propagation delay
       2. Bottleneck

                         

                          

12. Elements of bus design
    • Bus types
    • 1. Dedicated
         • Advantage: high throughput
         • Disadvantage: scale and cost increases
      2. Multiplexed
         • Advantage: fewer lines → saves space and cost
         • Disadvantage: more complex control, potential reduction in performance
    • Method of bus arbitration: more than one module may need control of the bus
    • • Centralized: a single hardware device, referred to as a bus controller or arbiter, is responsible for allocating time on the bus. The decive may be a separate module or part of the processor
      • • Daisy chain polling

• • • • • Advantage: scalable
        • Disadvantage: sensitive to circult failure
      • Counter polling

• • • • • Advantage: flexible priority, insensitive to circuit failure
        • Disadvantage: complex control
      • Separate request

• • • • • Advantage: rapid response, flexible priority
        • Disadvantage: too many lines, complex comtrol
    • Distributed: there is no central controller. Each module contains access control logic and the modules act together to share the bus
  • Timing: the way in which events are coordination on bus
  • • Synchronous: the occurrence of events is determined by clock signals
    • • Advantage: simple, easy to implement
      • Disadvantage: inflexible, velocity based on the slowest module(bottleneck)
    • Asynchronous: the occurrence of one event on a bus follows and depends on the occurrence of a previous event
    • • Advantage: request-responce, allowing fast and slow devices
      • Disadvantage: complex control
      • Types of asynchronous communication

• • • Half-synchronous
    • • Clock is needed
      • Wait line is needed
      • Allowing various speed modules to communicate harmoniously
      • Used for connecting low speed and larger speed difference devices
    • Separate
    • • Basic idea is:
      • • Separate bus cycle into two sub-cycles
        • In the first sub-cycle, master puts command, address and other information into the bus, then abandons the bus
        • In the second sub-cycle, slave begins to prepare data (select, decode, load), then applies the bus and sends the data
      • Advantage: avoiding bus idle waiting
      • Used for large computer
  • Bus width ≠ Bus bandwidth
  • • The width of data bus has an impact on system performance
    • The width of address bus has an impact on system capacity
  • Data transfer type