[2]Vivado中异步FIFO的实现和使用

FIFO应用：

• 1、在千兆以太网数据写入，往DDR3里面写数据时候
• 2、AD采样时钟和内部时钟不同时，需要FIFO进行转换
• 3、同频异相时也需要用FIFO进行转换

Vivado中FIFO generator的配置方法

1、

2、standard FIFOread mode读取时会延迟一个周期时钟，first word fall throughread mode 读取时没有延时时钟周期，给使能就有数据，read latency=0。

3、

read data count表示fifo中有多少个数据了。

异步FIFO实现

具体实现代码：

`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 2016/08/10 14:42:33// Design Name: // Module Name: fifo_timing// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //////////////////////////////////////////////////////////////////////////////////module fifo_timing(inputwiresclk,inputwirerst_n,inputwirer_clk,inputwiredata_v,inputwire[7:0]data_in,outputwiredata_ov,outputwire[15:0]data_out,output wirefifo_w_clk,outputwirefifo_r_clk,outputwirefifo_w_en,outputwire[7:0]fifo_w_data,inputwirefifo_full,outputwirefifo_r_en,inputwire[15:0]fifo_r_data,    inputwirefifo_empty,    inputwire[8:0]fifo_rd_count    );        wirefull;    wireempty;    // r_clk    regr_flag;    wire[8:0]rd_data_count;    reg[8:0]r_cnt;    wirerd_en;    assign fifo_w_clk = sclk;assign fifo_r_clk = r_clk;assign fifo_w_en = data_v & (~fifo_full);assign fifo_w_data = data_in;assign fifo_r_en = r_flag & (~fifo_empty);assign data_out = fifo_r_data;assign data_ov = r_flag;assignrd_en = r_flag;always @(posedge r_clk or negedge rst_n)if(rst_n == 1'b0)r_flag <= 1'b0;else if(r_flag == 1'b1 && r_cnt == 'd255 )r_flag <= 1'b0;else if(fifo_rd_count >= 'd255 && r_flag == 1'b0)r_flag <= 1'b1;always @(posedge r_clk or negedge rst_n)if(rst_n == 1'b0)r_cnt <='d0;else if(r_flag == 1'b1)r_cnt <= r_cnt + 1'b1;else r_cnt <='d0;assigndata_ov = r_flag;endmodule