基本结构（Basic Modelling）

基本结构（Basic Modelling）

一个基本的VHDL设计包含至少一个实体/结构体对。在大型的设计程序中，我们通常编写许多个实体/结构体对，并把他们组合起来，来实现一个完成的电路。

Every VHDL design description consists of at least one entity/architecture pair. In a large design, you will typically write many entity/architecture pairs and connect them together to form a complete circuit.

实体（Entity）

一个实体（entity）定义用来描述电路与外部世界的联系，它的输入和输出接口（端口（ports）和类属（generics））。在原理图设计中，实体定义就像是原理图中的一个电路逻辑块。

An entity declaration describes the circuit as it appears from the outside world, its input and output interfaces (ports and generics). In a schematic design, you might think of an entity declaration as being analogous to a block symbol on a schematic.
一个实体定义为电路提供完整的接口。你可以使用实体提供的接口信息，将其连接到其他更高层的电路中。
An entity declaration provides the complete interface for a circuit. You have all information you need to connect that circuit into other, higher-level circuits.

结构体（Architecture）

结构体（architecture）定义是一个最小VHDL设计中的第二部分。结构体描述了它所绑定的实体中，实际的功能或内容。你可以把结构体看作是，原理图设计中，一个高层电路逻辑块中的底层电路图。

The architecture declaration is the second part of a minimal VHDL design. The architecture describes the actual function, or contents, of the entity to which the architecture is bound. In a schematic design you can think that an architecture is analogous to a lower-level schematic referenced by the higher-level functional block symbol.
我们可以将许多子元件（sub-components）进行组合，来实现实体的具体功能。每一个子元件是许多实体的实例（instance），实例的接口通过信号（signals）连接在一起。一个信号代表一个电气连接，可以是一根线或者总线。端口映射（port map）用来连接信号和实例的端口，一个端口表示一个管脚。这种描述方法被称为结构性描述。
One way of describing the function of an entity is to describe how it is composed of sub-components. Each of the sub-components is an instance of some entity, and the interface of the instances are connected together using signals. A signal represents an electrical connection, a wire or a bus. A port map is used to connect signals to the ports of an instantiation, where a port represents a pin. This kind of description is called a structural.
另外，也可以用编程语言符号来描述实体的具体功能。这种方法被称为行为或功能性描述。这种行为性描述使用进程（processes）来实现。每个进程都是同步进行的。进程内的语句按照串行方式运行。
Another way of describing the function of an entity is in terms of programming language notations. This is called a behavioural or functional description. The behaviour is described using processes. Each process executes concurrently with respect to all other processes. Statements inside a process execute in sequential order.

配置（Configuration）

配置（configuration）语句用来指定结构体绑定到那个实体上，并且允许改变元件的连接（通过端口映射（port map）和类属映射（generic map））。

A configuration specifies which architecture is bound to which entity, and it allows to change the component connection (via a port map and generic map).
无论设计描述多么复杂，配置语句都是可以省略的。当没有声明配置语句时，VHDL为采用标准化的配置。例如，当实体中存在多个相关联的结构体时，最后一个结构体会自动被编译器绑定到实体上。
Configurations are always optional, no matter how complex the design description. When no configuration has been declared, the VHDL standard specifies a set of rules that provides a default configuration. For example, when an entity has more than one associated architecture, the last architecture compiled will be bound to the entity.