LVDS开发指南

LVDS学习笔记

该指南是我从各个文档中提取出来的关键点，为以后开发节省查阅资料的时间。

LVDS特点

• Low-voltage power supply compatibility
• Low noise generation
• High noise rejection
• Robust transmission signals
• Ability to be integrated into system level ICs
• LVDS technology allows products to address high data rates ranging
  from 100’s of Mbps to greater than 2 Gbps.
  

LVDS原理

关键参数

• 电压摆幅约350mv
• 电流驱动型，驱动电流3.5mA
• 端接电阻100ohm
• 差分走线阻抗90~130Ohm，推荐100Ohm +/-10%
• ANSI/TIA/EIA标准推荐最大传输速率为655Mbps（基于一系列的限制），理论值可达1.923Gbps（在无损介质中）。
• LVDS不依赖于特定的电压供应，例如5V。可以方便的移植到低电压供应的系统中，例如3.3V或2.5V。

PCB Layout tips

• Tip1：Try to keep stubs and uncontrolled impedance runs to <12 mm or 0.5 in.
• Tip2：avoid 90° turns since this causes impedance discontinuities; use 45° turns, radius or bevel PCB traces.
• Tip3：Use bypass capacitors at each package and make sure each power or ground trace is wide and short (do not use 50Ohm dimensions) with multiple vias to minimize inductance to the power planes.
• Tip4：Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.
• Tip5：Isolate fast edge rate CMOS/TTL signals from LVDS signals, otherwise the noisy single-ended CMOS/TTL signals may couple crosstalk onto the LVDS lines.It is best to put TTL and LVDS signals on a different layer(s), which should be isolated by the power and ground planes.
• Tip6：Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
• Tip7：Bypass each LVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best.
• Tip8：Power supply: A 4.7 μF or 10 μF, 35V tantalum capacitor works well between supply and ground. Choosing a capacitor value which best filters the largest power/ground frequency components (usually 100 MHz to 300 MHz) is best.The voltage rating of tantalum capacitors is critical and must not be less than 5 x VCC. Some electrolytic capacitors also work well.
• Tip7：VCC pins: One or two multi-layer ceramic (MLC) surface mount capacitors (0.1 μF and 0.01 μF) in parallel should be used between each VCC pin and ground if possible.
• Tip8：Power and ground should use wide (low impedance) traces — their job is to be a low impedance point. Do not use 50W design rules on power and ground traces.
• Tip9：Keep ground PCB return paths short and wide. Provide a return path that creates the smallest loop for the image currents to return.
• Tip10：Cables should employ a ground return wire connecting the grounds of the two systems.
• Tip11：Use two vias to connect to power and ground from bypass capacitor pads to minimize inductance
  effects. Surface mount capacitors are good as they are compact and can be located close to device pins.
• Tip12：he distance between the termination resistor and the receiver should be <7 mm (12 mm max.).
• Tip3：Using the edge-to-edge “S” distance between the traces of a pair, other separations can be defined:
  • The distance between two pairs should be >2S.
  • The distance between a pair and a TTL/CMOS signal should be >3S at a minimum. Even better,
  locate the TTL/CMOS signals on a different plane isolated by a ground plane.
  • If a guard ground trace or ground fill is used, it should be >2S away.

参考资料

【1】《LVDS Owner’s Manual》
http://download.csdn.net/detail/tianyake_1/9809417