PCIe学习笔记(33)--- PL
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Link capability register:
Max link speed (supported link speeds vector field bit x)
max link width (x1 ... x32)
link capability 2 register:
supportd link speeds vecotr
link status register:
current link speed
negotiated link width
link training
link control register:
link disable
retrain linnk
extended synch (?, forces the transmission of 4096 FTSs, 1024 TS1s)
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- PCIe学习笔记(33)--- PL
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