romInit.s分析

/* romInit.s - MCP8270 ROM initialization module */

 .data
 .globl  copyright_wind_river   /* zonewone注释：全局使用 */
 .long   copyright_wind_river   /* zonewone注释：.int 运行时给表达式赋值 */

/*zonewone注释： 系统初始化对不同的CPU,基本步骤是类似的。 系统初始化的主要步骤如下启动;   关闭中断;   放boot type到堆栈;   清空缓存
VxWorks 系统的 PowerPC BSP,  系统开机后执行的第一个函数 romInit(), 在ROM的起点*/

/*zonewone注释：
.data:包含用于该程序的预初始化数据  .text:包含实际代码（过去称为程序文本）
.opd:包含 “正式过程声明”，它用于辅助连接函数和指定程序的入口点（入口点就是要执行的代码中的第一条指令）*/

 

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().
*/

/*zonewone注释：CPU一上电就开始执行romInit( )函数，因此在romInit.s代码段中它必须是第一个函数。  跳转到C程序romStart( )函数中。*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "hlct8270.h"
#include "regs.h"
#include "sysLib.h"
#include "config.h"
#include "drv/timer/m8260Clock.h"
#include "drv/mem/m8260Siu.h"
#include "drv/mem/m8260Memc.h"

 /* internals */

 FUNC_EXPORT(_romInit)

 /*zonewone注释：start of system code  .globl _romInit ;  .type   _romInit,@function   没搞明白@fun的含义*/
 FUNC_EXPORT(romInit)       /* start of system code  */
 
 /* externals */

 FUNC_IMPORT(romStart) /* system initialization routine .extern romStart */

        _WRS_TEXT_SEG_START
         /*fill hard config word in image head*/
         .fill   8,1,HRDW_BYTE1   
         .fill   8,1,HRDW_BYTE2       
         .fill   8,1,HRDW_BYTE3
         .fill   8,1,HRDW_BYTE4 
         .fill   224,1,0
        .align  2   /*zonewone注释：使用“位置计数器”做相应的对齐操作*/

/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* /ss
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* /se
*/

FUNC_BEGIN(_romInit)  /*#define FUNC_LABEL(func)    func:*/
FUNC_BEGIN(romInit)
/*romInit:
_romInit:
*/
 bl cold  /* jump to the cold boot initialization  zonewone注释：冷启动*/
        nop
 bl start  /* jump to the warm boot initialization  zonewone注释：热启动*/
/*zonewone注释：b ADDRESS:跳转（或转移）到地址 ADDRESS 处的指令；
bl ADDRESS:对地址 ADDRESS 的子例程调用*/
/* copyright notice appears at beginning of ROM (in TEXT segment) */

 .ascii   "Copyright 1984-2001 Wind River Systems, Inc."
 .align 2
cold:
 li      r3, BOOT_COLD /* set cold boot as start type  (0x02) */
/*zonewone注释：li : 加载寄存器r3<-0x02; */
start:
        /* disable external interrupts (by zeroing out msr) */
 xor     r5,r5,r5 

/*zonewone注释：xor ra, rS, rb  . ra/rb :Instruction syntax used to identify a source GPR .
GPR:general-purpose registers*/
 isync

/*zonewone注释：
The isync instruction waits for all previous instructions to
complete and discards any prefetched instructions,
causing subsequent instructions to be refetched from
memory. 等待指令
*/

/*zonewone注释：SPR是特殊功能寄存器,DCR为设备控制寄存器,MSR机器状态寄存器*/
 mtmsr r5 /*Move to Machine State Register*/
 isync 

 /* invalidate and disable the MPU's data/instruction caches */
 
 mfspr r6, HID0  /*zonewone注释：Move from Special-Purpose Register  1008*/
 ori r5,r5,(_PPC_HID0_ICE | _PPC_HID0_DCE)  

/*zonewone注释：ori rA,rS,UIMM  Unsigned immediate value ; Instruction/Data Cache ennabe*/
 andc r6,r6,r5  /* clear cache enable bits in r6 */

/*zonewone注释：AND with Complement  andc ra, rs, rb. rs:respectively 分别 */
 mr r5,r6 /*move register. mr Rx, Ry = or Rx,Ry,Ry*/
 ori     r5,r5,(_PPC_HID0_ICE | _PPC_HID0_DCE | _PPC_HID0_ICFI | _PPC_HID0_DCFI) /*Instruction cache flash invalidate*/
 sync
 mtspr HID0,r5 

/* invalidate both caches with 2 stores ; zonewone注释：Move To Special Purpose Register*/
 mtspr HID0,r6  /* leaving them both disabled */
 isync

 mtspr   SPRG0,r3  /*zonewone注释：BOOT_COLD(0x02)->r3->SPRG0(272);*/
 bl romClearBATs                      /*clear IBAT/DBAT*/
 bl romInvalidateTLBs                /*clear TLBs*/  
 bl romClearSegs                      /*clear Seg.h*/
 bl romClearFPRegs                  /*clear FPreg*/
 mfspr   r3,SPRG0

        /* Zero-out registers: r0 & SPRGs */
 xor     r0,r0,r0
 mtspr SPRG0,r0
 mtspr SPRG1,r0
 mtspr SPRG2,r0
 mtspr SPRG3,r0

 /* MSR: clear EE,DR,IR -- set ME,RI */
        mfmsr   r4   /*0->r5->r4*/
 ori r4,r0,0x1002
 mtmsr   r4   /*0x1002*/
 isync

 lis r4, HIADJ(INTERNAL_MEM_MAP_ADDR+0x10000)
/*Internal Memory Map base Address; zonewone注释：
#define HIADJ(arg)      %hiadj(arg) ;#define HIADJ(arg) arg@ha 没搞明白什么问题*/
 sync

 /*
  * initialize the SIU.
  */

 bl romSiuInit     /SIU:/
 /*caculate flash absolute address and jump to that address*/
 xor     r3, r3,r3
 lwz     r3, INIT_OR0(r4)
 li      r5, 0x7fff
 and     r3, r3, r5
 stw     r3, INIT_OR0(r4)

 lis     r3,ROM_BASE_ADRS@h
/*zonewone注释：  #define ROM_BASE_ADRS         0xFF000000      base address of ROM    config.h */
 ori     r3,r3,ROM_BASE_ADRS@l
 addi    r3,r3,real_flash - _romInit + EXC_OFF_SYS_RESET   /*#define EXC_OFF_SYS_RESET     0x0100*/
 mtlr    r3
/*Link Register (LR) mtlr Rx mtspr 8,Rx mflr Rx mfspr Rx,8*/
 blr
 /*
  * initialize the MEMC -- chip selects and SDRAM.
  */
real_flash:
 bl romMemcInit

 /*
  * Initialize Instruction and Data Caches
  */

 bl romCacheInit

 /* initialize the stack pointer */

 lis sp, HIADJ(STACK_ADRS)
 addi sp, sp, LO(STACK_ADRS)
 
 /* go to C entry point */

 addi sp, sp, -FRAMEBASESZ  /* get frame stack */

 /*
  * calculate C entry point: routine - entry point + ROM base
  * routine = romStart = R6
  * entry point = romInit = R7
  * ROM base = ROM_TEXT_ADRS = R8
  * C entry point: R6 - R7 + R8
  */

 lis r6, HIADJ(romStart)
 addi r6, r6, LO(romStart) /* zonewone注释：load R6 with C entry point r6 = romStart*/

 lis r7, HIADJ(romInit)        /* zonewone注释：load R7  = romInit*/
 addi r7, r7, LO(romInit)

 lis r8, HIADJ(ROM_TEXT_ADRS)
 addi r8, r8, LO(ROM_TEXT_ADRS)

 sub r6, r6, r7 /* zonewone注释：routine - entry point  ;r6=r6-r7*/
 add r6, r6, r8  /* zonewone注释：+ ROM base ;r6=r6+r8 */

 mtlr r6      /* zonewone注释：move C entry point to LR  */
 blr          /* zonewone注释：jump to the C entry point */

FUNC_END(romInit)
FUNC_END(_romInit)

/***************************************************************************
*
* romClearBATs - clearing all the BAT's register.
*
* This routine will zero the BAT's register.
*
* SYNOPSIS
* /ss
* void romClearBATs
*     (
*     void
*     )
* /se
*
* SEE ALSO: romInvalidateTLBs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romClearBATs)
  /* zero out the BAT registers */
 xor  r5,r5,r5 /*zonewone注释：r5 清零*/
 isync
 mtspr IBAT0U,r5 /* clear all upper BATS first ;Instruction BAT Registers(528)*/
 mtspr IBAT1U,r5
 mtspr IBAT2U,r5
 mtspr IBAT3U,r5
 mtspr DBAT0U,r5
 mtspr DBAT1U,r5
 mtspr DBAT2U,r5
 mtspr DBAT3U,r5

 mtspr IBAT0L,r5 /* then clear lower BATS */
 mtspr IBAT1L,r5
 mtspr IBAT2L,r5
 mtspr IBAT3L,r5
 mtspr DBAT0L,r5
 mtspr DBAT1L,r5
 mtspr DBAT2L,r5
 mtspr DBAT3L,r5
 isync

 blr
FUNC_END(romClearBATs)

/***************************************************************************
*
* romClearSegs - clearing all the SEG's register.
*
* This routine will zero the SEG's register.
*
* SYNOPSIS
* /ss
* void romClearSegs
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romClearSegs)
  /* Init the Segment registers */
 xor r5, r5, r5
 isync
 mtsr 0,r5
 mtsr 1,r5
 mtsr 2,r5
 mtsr 3,r5
 mtsr 4,r5
 mtsr 5,r5
 mtsr 6,r5
 mtsr 7,r5
 mtsr 8,r5
 mtsr 9,r5
 mtsr 10,r5
 mtsr 11,r5
 mtsr 12,r5
 mtsr 13,r5
 mtsr 14,r5
 mtsr 15,r5
 isync

 blr
FUNC_END(romClearSegs)

/***************************************************************************
*
* romInvalidateTLBs - invalidate the TLB's.
*
* This routine will invalidate the TLB's.
*
* SYNOPSIS
* /ss
* void romInvalidateTLBs
*     (
*     void
*     )
* /se
*
* SEE ALSO: romClearBATs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInvalidateTLBs)
 isync
 /* invalidate entries within both TLBs */
 li r5,128
 mtctr r5   /* zonewone注释：CTR = 32; Count Register (CTR) */
 xor     r5,r5,r5
 isync    /* context sync req'd before tlbie */

tlbloop:
 tlbie r5        
/*zonewone注释：TLB Invalidate Entry  Translation lookaside buffer  为了加速MMU访问，使用了tlb
为了加速PPC601的页基址变换,PPC601中设计了一个256项2路组相关联的指令数据混合TLB(Translation Loo
kaside Buffer)。PPC601的块地址变换机制允许进行大小可变的块地址映射,块的大小由128KB到8MB。*/
/*Use the tlbie or tlbia instruction to ensure that the TLB no longer contains a mapping for a particular virtual page.*/

 sync        /* sync instr req'd after tlbie      */
 addi r5,r5,0x1000 /* increment bits 15-19              */
 bdnz tlbloop   /* decrement CTR, branch if CTR != 0 */
 isync
 blr
FUNC_END(romInvalidateTLBs)

/***************************************************************************
*
* romClearFPRegs - initialize the FPU's registers
*
* This routine will initialize the FPU's registers.
*
* SYNOPSIS
* /ss
* void romClearFPRegs
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romClearFPRegs)
        mflr r30  /*(equivalent to: mfspr Rx, 8)*/
 
        /* Turn on FP */
        li      r3,_PPC_MSR_FP  /* floating-point available */
        mtmsr   r3
        sync

        /* Init the floating point control/status register */
        mtfsfi  7,0x0
        mtfsfi  6,0x0
        mtfsfi  5,0x0
        mtfsfi  4,0x0
        mtfsfi  3,0x0
        mtfsfi  2,0x0
        mtfsfi  1,0x0
        mtfsfi  0,0x0
        isync

        /* Initialize the floating point data registers to a known state */

        bl      ifpdrValue
        .long   0x3f800000      /* 1.0 */

ifpdrValue:
        mflr    r3 /*(equivalent to: mfspr Rx, 8)*/
        lfs     f0,0(r3)  /*Load Floating-Point Single*/
        lfs     f1,0(r3)
        lfs     f2,0(r3)
        lfs     f3,0(r3)
        lfs     f4,0(r3)
        lfs     f5,0(r3)
        lfs     f6,0(r3)
        lfs     f7,0(r3)
        lfs     f8,0(r3)
        lfs     f9,0(r3)
        lfs     f10,0(r3)
        lfs     f11,0(r3)
        lfs     f12,0(r3)
        lfs     f13,0(r3)
        lfs     f14,0(r3)
        lfs     f15,0(r3)
        lfs     f16,0(r3)
        lfs     f17,0(r3)
        lfs     f18,0(r3)
        lfs     f19,0(r3)
        lfs     f20,0(r3)
        lfs     f21,0(r3)
        lfs     f22,0(r3)
        lfs     f23,0(r3)
        lfs     f24,0(r3)
        lfs     f25,0(r3)
        lfs     f26,0(r3)
        lfs     f27,0(r3)
        lfs     f28,0(r3)
        lfs     f29,0(r3)
        lfs     f30,0(r3)
        lfs     f31,0(r3)
        sync

        /*
         *     Set MPU/MSR to a known state
         *     Turn off FP
         */

        andi.  r3,r3,0
        sync
        mtmsr  r3
        isync
 
        mtlr   r30
        bclr   20,0  /*zonewone注释：Return to caller;Branch Conditional to Link Register */
FUNC_END(romClearFPRegs)

/***************************************************************************
*
* romSiuInit - initialize the general SIU
*
* This routine initialize the System Interfac Unit
*
* SYNOPSIS
* /ss
* void romSiuInit
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romSiuInit)
 /*we initial hlct8270 bus here*/
 
 li      r9,0x01
 stw     r9,INIT_SCCR(r4) /*BRG clock freq: Divide by 16(normal operation)*/
/*zonewone注释：
Store Word Indexed
stw RS,D(RA)           if RA = 0 then b
<- 0    else b
(RA)
EA
b + EXTS(D)     MEM(EA, 4)
<-(RS)
*/
 
  lis     r9,0xFFFF   /*Load a 16-bit signed immediate value, shifted left by 16 bits, into register Rx.  (equivalent to: addis Rx,0,value)*/
 ori     r9,r9,0xFF03      /*Bus monitor is disabled*/
 stw     r9,INIT_SYPCR(r4) /* SYPCR */

  lis     r9,0x0000
 ori     r9,r9,0x0000    
 stw     r9,INIT_BCR(r4)  /* BCR EBM=0,APD=0,NPQM=000*/
 
 li      r9,0x23     /*DBGD=1,PRKM=0011,now 60x bus Parking master must be PCI bridge*/
 stb     r9,INIT_PPC_ACR(r4) /*60x Arbiter Configuration Register*/

 /*config 60x Arbitration-Level Register*/
  lis     r9,0x3012
 ori     r9,r9,0x6894
 stw     r9,INIT_PPC_ALRH(r4) /*PCI bridge should have a higher priority
                              than all other 60x bus master to avoid dead lock*/
  lis     r9,0x57ab
 ori     r9,r9,0xcdef
 stw     r9,INIT_PPC_ALRL(r4)

 lis     r9, 0x4064
 ori     r9,r9,0xC000
 stw     r9,INIT_SIUMCR(r4) /* SIUMCR */

 bclr   20,0
FUNC_END(romSiuInit)

/***************************************************************************
*
* romMemcInit - initialize the memory controller and SDRAM
*
* This routine initialize the memory controller and SDRAM
*
* SYNOPSIS
* /ss
* void romMemcInit
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romMemcInit)

        mfspr r30,LR  /*zonewone注释：LR->r3*/

 bl     romChipSelectInit

 /* set the memory periodic timer prescaler 66Mhz */
 li r5,0x3200
 sth     r5,INIT_MPTPR(r4)

 bl romMemcSdram60xBusInit
  /*bl romMemcSdramLocalBusInit*/

 mtspr LR,r30
 bclr 20,0
FUNC_END(romMemcInit)

/***************************************************************************
*
* romChipSelectInit - initialize the Scout chip select
*
* This routine initialize the Scout chip select
*
* SYNOPSIS
* /ss
* void romChipSelectInit
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romChipSelectInit)

         mfspr r29,LR

 /* NOTE:
  * It's important to note the order in which OR0 and BR0 are programmed.
  * When coming out of reset CS0 is the global chip select, OR0 MUST be
  * programmed AFTER BR0. In all other cases ORx should be programmed first.
  */

 /*
  * CS0: 16Meg, 32-bit Flash
  */
 lis r5,0xFF00
 ori r5,r5,0x1001
 stw r5,INIT_BR0(r4)

 lis r5,0xFF00
 ori r5,r5,0x0CF6
 stw r5,INIT_OR0(r4)
 
 /*
  * CS1: to 60x Bus SDRAM.
  */
 lis r5,0x0000
 ori r5,r5,0x0041
 stw r5,INIT_BR1(r4)

 lis r5,0xF800  /* CS1 -> 128M @ 0x00000000 */
 ori r5,r5,0x2b10
 stw r5,INIT_OR1(r4)

 /*
  * CS2: to DPRAM.
  */
 lis r5,0x2000
 ori r5,r5,0x1001
 stw r5,INIT_BR2(r4)

 lis r5,0xFF00  /* DPRAM */
 ori r5,r5,0x0c64
 stw r5,INIT_OR2(r4)

 xor r5,r5,r5
 stw r5,INIT_BR3(r4)
 stw r5,INIT_BR4(r4)
 stw r5,INIT_BR5(r4)
 stw r5,INIT_BR6(r4)   
 stw r5,INIT_BR7(r4)
 stw r5,INIT_BR8(r4)
 stw r5,INIT_BR9(r4)
 stw r5,INIT_BR10(r4)
 stw r5,INIT_BR11(r4)

 mtspr   LR,r29
 bclr    20,0
FUNC_END(romChipSelectInit)

/***************************************************************************
*
* romMemcSdram60xBusInit - initialize 60x Bus SDRAM.
*
* This routine initialize 60x Bus SDRAM.
*
* SYNOPSIS
* /ss
* void romMemcSdram60xBusInit
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romMemcSdram60xBusInit)

 mfspr r29,LR
        li      r0,0
 lis r6,0x0000
 /*Load a 16-bit signed immediate value, shifted left by 16 bits, into register Rx.*/

 /* set the 60x bus-assigned SDRAM refresh timer */

 li r5,0x2000
 sth     r5,INIT_MPTPR(r4) 
/* zonewone注释：Store Halfword D-form if RA = 0 then b
0 e  lse b
(RA)
EA
b + EXTS(D) MEM(EA, 2)
(RS)48:63
EXTS(x) Result of extending x on the left with sign bits
MEM(x, y) Contents of y bytes of storage starting at address x. In 32-bit mode the high-order 32 bits of the 64-bit value x are ignored.
Memory periodic timer prescaler*/

 li r5,0x0010
 stb     r5,INIT_PSRT(r4)  /*60x bus-assigned SDRAM refresh timer*/

        lis r5,0x83AD  /* Issue Precharge All-Banks command */
        ori r5,r5,0xA466
        stw r5,INIT_PSDMR(r4)  /*60x bus SDRAM mode register*/

 /*
  * Initialize SDRAM.
  */
        lis r5,0xABAD  /* Issue Precharge All-Banks command */
        ori r5,r5,0xA466
        stw r5,INIT_PSDMR(r4)
       
        li r5,0xFF
        stb r5,0(r6)

        lis r5,0x8BAD  /* Issue single CBR Refresh command */
        ori r5,r5,0xA466
        stw r5,INIT_PSDMR(r4)
       
 /* Issue 8 0xFF writes to address 0 */
        li r5,0xFF
        stb     r5,0(r6)
        stb     r5,1(r6)
        stb r5,2(r6)
        stb r5,3(r6)
        stb r5,4(r6)
        stb r5,5(r6)
        stb r5,6(r6)
        stb r5,7(r6)

        lis r5,0x9BAD  /* Issue Mode Set command */
        ori r5,r5,0xA466
        stw r5,INIT_PSDMR(r4)
       
        li r5,0xFF
        stb r5,0x110(r6)

        lis r5,0xDBAD  /* Issue Mode Set command */
        ori r5,r5,0xA466
        stw r5,INIT_PSDMR(r4)

        lis     r5,0xC4AD  /* Issue Normal Operation command */
        ori r5,r5,0xA466
        stw r5,INIT_PSDMR(r4)                       

 mtspr LR,r29
 bclr 20,0
FUNC_END(romMemcSdram60xBusInit)

/***************************************************************************
*
* romMemcSdramLocalBusInit - initialize Local Bus SDRAM.
*
* This routine initialize 60x Bus SDRAM.
*
* SYNOPSIS
* /ss
* void romMemcSdramLocalBusInit
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romMemcSdramLocalBusInit)
 mfspr   r29,LR
        li      r0,0
 lis r6,0x3800

 li r5,0x0008
 stb r5,INIT_LURT(r4)

 li r5,0x000E
 stb     r5,INIT_LSRT(r4)

 lis r5,0x2866
 ori r5,r5,0xA552
 stw r5,INIT_LSDMR(r4)

        li r5,0xFF
        stb     r5,0(r6)

 lis r5,0x0866
 ori r5,r5,0xA552
 stw r5,INIT_LSDMR(r4)

        /* Issue 8 0xFF writes to address 0x10000000 */
        li r5,0xFF
        stb     r5,1(r6)
        stb r5,2(r6)
        stb r5,3(r6)
        stb r5,4(r6)
        stb r5,5(r6)
        stb r5,6(r6)
        stb r5,7(r6)
        stb r5,8(r6)

 lis r5,0x1866
 ori r5,r5,0xA552
 stw r5,INIT_LSDMR(r4)

        li r5,0xFF
        stb     r5,9(r6)

 lis r5,0x4066
 ori r5,r5,0xA552
 stw r5,INIT_LSDMR(r4)

 mtspr LR,r29
 bclr 20,0
FUNC_END(romMemcSdramLocalBusInit)

/***************************************************************************
*
* romCacheInit - initialize the instruction cache
*
* This routine initialize the instruction cache.
*
* SYNOPSIS
* /ss
* void romCacheInit
*     (
*     void
*     )
* /se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romCacheInit)
 /* turn the instruction cache ON for faster FLASH ROM boots */

 mfspr r5,HID0
 ori r5,r5,_PPC_HID0_ICE
 isync

 /*
  * The setting of the instruction cache enable (ICE) bit must be
  * preceded by an isync instruction to prevent the cache from being
  * enabled or disabled while an instruction access is in progress.
  */

 mtspr HID0,r5
 sync
 isync
 bclr 20,0
FUNC_END(romCacheInit)