uboot 分析之二 start_armboot
来源：互联网 发布：马克斯cms下载 编辑：程序博客网 时间：2024/05/21 19:07
在分析start_armboot 之前先来解决上节遗留下来的两个问题。
一、lowlevel_init 对哪些设备进行了初始化
二、copy_uboot_to_ram 如何复制UBoot
先上代码
#include <config.h>#include <version.h>#include <s3c6410.h>#include "mini6410_val.h"_TEXT_BASE:.wordTEXT_BASE.globl lowlevel_initlowlevel_init:movr12, lr/* LED on only #8 */ldrr0, =ELFIN_GPIO_BASEldrr1, =0x55540000strr1, [r0, #GPNCON_OFFSET]ldrr1, =0x55555555strr1, [r0, #GPNPUD_OFFSET]ldrr1, =0xf000strr1, [r0, #GPNDAT_OFFSET]ldrr0, =ELFIN_GPIO_BASEldrr1, =0x1strr1, [r0, #GPECON_OFFSET]ldrr1, =0x0strr1, [r0, #GPEDAT_OFFSET]ldrr0, =ELFIN_GPIO_BASEldrr1, =0x2A5AAAAAstrr1, [r0, #GPPCON_OFFSET]ldrr1, =0x0strr1, [r0, #GPPDAT_OFFSET]ldrr1, =0x55555555strr1, [r0, #MEM1DRVCON_OFFSET]/* Disable Watchdog */ /*关看门狗*/ldrr0, =0x7e000000@0x7e004000orrr0, r0, #0x4000movr1, #0strr1, [r0]@ External interrupt pending clear /*清外部中断标志位*/ldrr0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET)/*EINTPEND*/ldrr1, [r0]strr1, [r0]ldrr0, =ELFIN_VIC0_BASE_ADDR @0x71200000ldrr1, =ELFIN_VIC1_BASE_ADDR @0x71300000@ Disable all interrupts (VIC0 and VIC1) /*禁用VIC0、VIC1*/mvnr3, #0x0strr3, [r0, #oINTMSK]strr3, [r1, #oINTMSK]@ Set all interrupts as IRQ /*设置所有中断为IRQ*/movr3, #0x0strr3, [r0, #oINTMOD]strr3, [r1, #oINTMOD]@ Pending Interrupt Clear /*清中断标志位*/movr3, #0x0strr3, [r0, #oVECTADDR]strr3, [r1, #oVECTADDR]/* init system clock */ /*初始化系统时钟*/bl system_clock_init/* for UART */ /*串口初始化*/bl uart_asm_init#if defined(CONFIG_NAND) /*初始化NAND*/ /* simple init for NAND */bl nand_asm_init#endifblmem_ctrl_asm_init /*初始化DRAM*/#if 1 ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) /*RST_STAT Check*/ ldr r1, [r0] bic r1, r1, #0xfffffff7 cmp r1, #0x8 beq wakeup_reset /*Reset by SLEEP mode wake-up */#endif1:ldrr0, =ELFIN_UART_BASE /*输出 'K'*/ldrr1, =0x4b4b4b4bstrr1, [r0, #UTXH_OFFSET]//ldrr0, =ELFIN_UART_BASE//ldrr1, =0x4b4b4b4b//strr1, [r0, #UTXH_OFFSET]movlr, r12movpc, lr /*跳回start.s*/#if 1wakeup_reset:/*Clear wakeup status register*/ldrr0, =(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)ldrr1, [r0]strr1, [r0] /*LED test*/ ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x3000 str r1, [r0, #GPNDAT_OFFSET]/*Load return address and jump to kernel*/ldrr0, =(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)ldrr1, [r0]/* r1 = physical address of s3c6400_cpu_resume function*/movpc, r1/*Jump to kernel (sleep-s3c6400.S)*/nopnop#endif/* * system_clock_init: Initialize core clock and bus clock. * void system_clock_init(void) */system_clock_init:ldrr0, =ELFIN_CLOCK_POWER_BASE@0x7e00f000ldrr1, [r0, #OTHERS_OFFSET] @0x7e00f900movr2, #0x40orrr1, r1, r2 strr1, [r0, #OTHERS_OFFSET] /*SYS CLOCK SELECT IN CMU 1 : DOUTAPLL*/nopnopnopnopnopldrr2, =0x80orrr1, r1, r2strr1, [r0, #OTHERS_OFFSET] /*SYNCMODEREQ to ARM 1: Synchronous mode */check_syncack:ldrr1, [r0, #OTHERS_OFFSET]ldrr2, =0xf00andr1, r1, r2cmpr1, #0xf00bnecheck_syncack /*SYNC mode acknowledge (Read Only) */movr1, #0xff00orrr1, r1, #0xffstrr1, [r0, #APLL_LOCK_OFFSET] /*Required period to generate a stable clock output*/strr1, [r0, #MPLL_LOCK_OFFSET]strr1, [r0, #EPLL_LOCK_OFFSET]/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) *//* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) *//* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */#if defined(CONFIG_CLKSRC_CLKUART)ldr r1, [r0, #CLK_DIV2_OFFSET]bicr1, r1, #0x70000orrr1, r1, #0x30000strr1, [r0, #CLK_DIV2_OFFSET]#endifldr r1, [r0, #CLK_DIV0_OFFSET]/*Set Clock Divider*/bicr1, r1, #0x30000bicr1, r1, #0xff00bicr1, r1, #0xffldrr2, =CLK_DIV_VALorrr1, r1, r2strr1, [r0, #CLK_DIV0_OFFSET]ldrr1, =APLL_VALstrr1, [r0, #APLL_CON_OFFSET]ldrr1, =MPLL_VALstrr1, [r0, #MPLL_CON_OFFSET]ldrr1, =0x80200203/* FOUT of EPLL is 96MHz */strr1, [r0, #EPLL_CON0_OFFSET]ldrr1, =0x0strr1, [r0, #EPLL_CON1_OFFSET]ldrr1, [r0, #CLK_SRC_OFFSET]/* APLL, MPLL, EPLL select to Fout */#if defined(CONFIG_CLKSRC_CLKUART)ldrr2, =0x2007#elseldrr2, =0x7#endiforrr1, r1, r2strr1, [r0, #CLK_SRC_OFFSET]/* wait at least 200us to stablize all clock */movr1, #0x100001:subsr1, r1, #1bne1b#ifdef CONFIG_SYNC_MODE/* Synchronization for VIC port */ldrr1, [r0, #OTHERS_OFFSET]orrr1, r1, #0x20strr1, [r0, #OTHERS_OFFSET]movpc, lr/* * uart_asm_init: Initialize UART in asm mode, 115200bps fixed. * void uart_asm_init(void) */uart_asm_init:/* set GPIO to enable UART */@ GPIO setting for UARTldrr0, =ELFIN_GPIO_BASEldrr1, =0x22222222str r1, [r0, #GPACON_OFFSET]ldrr1, =0x2222str r1, [r0, #GPBCON_OFFSET]ldrr0, =ELFIN_UART_CONSOLE_BASE@0x7F005000movr1, #0x0strr1, [r0, #UFCON_OFFSET]strr1, [r0, #UMCON_OFFSET]movr1, #0x3 @was 0.strr1, [r0, #ULCON_OFFSET]#if defined(CONFIG_CLKSRC_CLKUART)ldrr1, =0xe45/* UARTCLK SRC = 11 => EXT_UCLK1*/#elseldrr1, =0x245/* UARTCLK SRC = x0 => PCLK */#endifstrr1, [r0, #UCON_OFFSET]#if defined(CONFIG_UART_50)ldrr1, =0x1A#elif defined(CONFIG_UART_66)ldrr1, =0x22#elseldrr1, =0x1A#endifstrr1, [r0, #UBRDIV_OFFSET]#if defined(CONFIG_UART_50)ldrr1, =0x3#elif defined(CONFIG_UART_66)ldrr1, =0x1FFF#elseldrr1, =0x3#endifstrr1, [r0, #UDIVSLOT_OFFSET]ldrr1, =0x4f4f4f4fstrr1, [r0, #UTXH_OFFSET]@'O' /*串口输出'O'*/movpc, lr/* * Nand Interface Init for SMDK6400 */nand_asm_init: /*NAND Flash Configuration register*/ldrr0, =ELFIN_NAND_BASEldrr1, [r0, #NFCONF_OFFSET]orrr1, r1, #0x70orrr1, r1, #0x7700str r1, [r0, #NFCONF_OFFSET]ldrr1, [r0, #NFCONT_OFFSET]orrr1, r1, #0x03str r1, [r0, #NFCONT_OFFSET]movpc, lr#ifdef CONFIG_ENABLE_MMU/* * MMU Table for SMDK6400 *//* form a first-level section entry */.macro FL_SECTION_ENTRY base,ap,d,c,b.word (\base << 20) | (\ap << 10) | \ (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1).endm.section .mmudata, "a".align 14// the following alignment creates the mmu table at address 0x4000..globl mmu_tablemmu_table:.set __base,0// 1:1 mapping for debugging.rept 0xA00FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr// access is not allowed..rept 0xC00 - 0xA00.word 0x00000000.endr// 128MB for SDRAM 0xC0000000 -> 0x50000000.set __base, 0x500.rept 0xC80 - 0xC00FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr// access is not allowed..rept 0x1000 - 0xc80.word 0x00000000.endr#endif进行了一些最主要初始化包括系统时钟、串口、nandflash、DRAM。
下面来看另一个代码 copy_uboot_to_ram
int copy_uboot_to_ram (void){int large_block = 0;int i;vu_char id; NAND_ENABLE_CE(); /*Enable nandchip select*/ NFCMD_REG = NAND_CMD_READID; /*read id*/ NFADDR_REG = 0x00;/* wait for a while */ for (i=0; i<200; i++);id = NFDATA8_REG;id = NFDATA8_REG;if (id > 0x80) large_block = 1;/* read NAND Block. * 128KB ->240KB because of U-Boot size increase. by scsuh * So, read 0x3c000 bytes not 0x20000(128KB). */return nandll_read_blocks(CFG_PHY_UBOOT_BASE, UBOOTBINSIZE, large_block); /** Read data from NAND.*/} static int nandll_read_blocks (ulong dst_addr, ulong size, int large_block){ uchar *buf = (uchar *)dst_addr; int i;uint page_shift = 9; /* 512bytes/page */if (large_block)page_shift = 11; /* 2k/page */ /* Read pages */ for (i = 0; i < (UBOOTBINSIZE>>page_shift); i++, buf+=(1<<page_shift)) { // for (i = 0; i < (0x3c000>>page_shift); i++, buf+=(1<<page_shift)) { nandll_read_page(buf, i, large_block); } return 0;}- uboot 分析之二 start_armboot
- uboot 分析之二 start_armboot()函数
- uboot 二 之start_armboot
- uboot之start_armboot分析1
- uboot之start_armboot分析2
- uboot之start_armboot分析3
- uboot之start_armboot分析4
- uboot分析--start_armboot
- Uboot start_armboot
- uboot第2阶段分析 start_armboot
- uboot第2阶段分析 start_armboot--转帖
- uboot第2阶段分析 start_armboot
- uboot第2阶段分析 start_armboot
- uboot第2阶段分析 start_armboot
- uboot源码分析——start_armboot
- uboot源码分析——start_armboot()函数
- Uboot之二 ~~~ Uboot.lds的分析
- DECLARE_GLOBAL_DATA_PTR、gd_t、bd_t及uboot中 start_armboot 代码分析
- NoSuchMethodError: org.apache.commons.collections.CollectionUtils.isNotEmpty(Ljava/util/Collecti
- 大并发量,大数据量基于SSH应用程序架构问题
- linux nc命令操作memcache
- 黑马程序员-高新技术day 2
- 关于SSH框架的集群，负载均衡，以及缓存集群的配置搭建
- uboot 分析之二 start_armboot
- Zend Studio 快捷键，支持7.0以上的版本
- 【堆+区间DP】Orz细菌(orz)
- 使用异或模式画橡皮线
- ASP.net性能优化
- Linux USB 鼠标驱动程序解析
- 键盘KeyCode值列表
- Java注释(Annotation)详解
- 理解 JavaScript 的 this 关键字（代码）
