关于EDA自动售货机的设计

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY moore  IS
  PORT
(clk ,reset:IN std_logic;
state_inputs:IN std_logic_vector(0 TO 1);
comb_outputs:OUT std_logic_vector(0 TO 1)
);
END moore;
ARCHITECTURE be OF moore  IS
  TYPE fsm_st  IS (S0,S1,S2,S3,S4);--状态的枚举类型定义
  SIGNAL current_state,next_state:fsm_st ;--状态信号的定义
BEGIN
Reg:PROCESS(reset,clk )                     --时序进程
    BEGIN
    IF reset='1' THEN current_state<=S0;   --异步复位
    ELSIF rising_edge(clk )THEN
    current_state<=next_state;              --状态转换
    END IF;
    END PROCESS reg;
corn:PROCESS(current_state,state_Inputs)    --组合进程
    BEGIN
CASE current_state IS
  WHEN S0 => comb_outputs<="00";               --现态S0
    IF state_inputs="00" THEN next_state<=S0;--输入不同,次态不同
    ELSIF state_inputs="01" THEN next_state<=S1;
    ELSIF state_inputs="10" THEN next_state<=S2;
    END IF;
  WHEN S1=>comb_outputs<="00";                --现态Sl  
    IF state_inputs="00" THEN next_state<=S1;--输入不同,次态不同
    ELSIF state_inputs="01" THEN next_state<=S2;
    ELSIF state_inputs="10" THEN next_state<=S3;
    END IF;
WHEN S2 =>comb_outputs<="00";                --现态S2
    IF state_inputs="00" THEN next_state<=S2;--输入不同,次态不同
    ELSIF state_inputs="01" THEN next_state<=S3;
    ELSIF state_inputs="10" THEN next_state<=S4;
    END IF;
WHEN S3 =>comb_outputs<="10";             --现态S3
    IF state_inputs="00" THEN next_state<=S0;--输入不同,次态不同
    ELSIF state_inputs="01" THEN next_state<=S1;
    ELSIF state_inputs="10" THEN next_state<=S2;
    END IF;
WHEN S4=>comb_outputs<="11";          --现态S4
    IF state_inputs="00" THEN next_state<=S0;--输入不同,次态不同
    ELSIF state_inputs="01" THEN next_state<=S1;
    ELSIF state_inputs="10" THEN next_state<=S2;
    END IF;
END CASE;
END PROCESS corn;


END be;