移位寄存器模型.v

 

module dlatch(q,d,clk,reset);input d,clk,reset;output q;reg q;always @(posedge clk) beginif(reset) q<=0; else q<=d; endendmodulemodule sreg(q,d,clk,reset);input d,clk,reset;output q;parameter DELAY  = 4;wire [DELAY : 0]w;assign w[0] = d;assign q = w[DELAY];genvar i;generate for(i = 0;i<DELAY;i = i+ 1) begin:grdlatch lc(.q(w[i+1]),.d(w[i]),.clk(clk),.reset(reset));endendgenerateendmodule